1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * Corenet DS style board configuration file 9 */ 10 #ifndef __T4QDS_H 11 #define __T4QDS_H 12 13 #define CONFIG_DISPLAY_BOARDINFO 14 #define CONFIG_CMD_REGINFO 15 16 /* High Level Configuration Options */ 17 #define CONFIG_BOOKE 18 #define CONFIG_E500 /* BOOKE e500 family */ 19 #define CONFIG_E500MC /* BOOKE e500mc family */ 20 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 21 #define CONFIG_MP /* support multiple processors */ 22 23 #ifndef CONFIG_SYS_TEXT_BASE 24 #define CONFIG_SYS_TEXT_BASE 0xeff40000 25 #endif 26 27 #ifndef CONFIG_RESET_VECTOR_ADDRESS 28 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 29 #endif 30 31 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 32 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 33 #define CONFIG_FSL_IFC /* Enable IFC Support */ 34 #define CONFIG_PCI /* Enable PCI/PCIE */ 35 #define CONFIG_PCIE1 /* PCIE controler 1 */ 36 #define CONFIG_PCIE2 /* PCIE controler 2 */ 37 #define CONFIG_PCIE3 /* PCIE controler 3 */ 38 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 39 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 40 41 #define CONFIG_SYS_SRIO 42 #define CONFIG_SRIO1 /* SRIO port 1 */ 43 #define CONFIG_SRIO2 /* SRIO port 2 */ 44 45 #define CONFIG_FSL_LAW /* Use common FSL init code */ 46 47 #define CONFIG_ENV_OVERWRITE 48 49 /* 50 * These can be toggled for performance analysis, otherwise use default. 51 */ 52 #define CONFIG_SYS_CACHE_STASHING 53 #define CONFIG_BTB /* toggle branch predition */ 54 #ifdef CONFIG_DDR_ECC 55 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 56 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 57 #endif 58 59 #define CONFIG_ENABLE_36BIT_PHYS 60 61 #define CONFIG_ADDR_MAP 62 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 63 64 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 65 #define CONFIG_SYS_MEMTEST_END 0x00400000 66 #define CONFIG_SYS_ALT_MEMTEST 67 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 68 69 /* 70 * Config the L3 Cache as L3 SRAM 71 */ 72 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 73 #define CONFIG_SYS_L3_SIZE (512 << 10) 74 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 75 #ifdef CONFIG_RAMBOOT_PBL 76 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 77 #endif 78 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 79 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 80 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 81 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 82 83 #define CONFIG_SYS_DCSRBAR 0xf0000000 84 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 85 86 /* 87 * DDR Setup 88 */ 89 #define CONFIG_VERY_BIG_RAM 90 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 91 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 92 93 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 94 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 95 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 96 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 97 98 #define CONFIG_DDR_SPD 99 #define CONFIG_SYS_FSL_DDR3 100 101 102 /* 103 * IFC Definitions 104 */ 105 #define CONFIG_SYS_FLASH_BASE 0xe0000000 106 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 107 108 109 #ifdef CONFIG_SPL_BUILD 110 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 111 #else 112 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 113 #endif 114 115 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 116 #define CONFIG_MISC_INIT_R 117 118 #define CONFIG_HWCONFIG 119 120 /* define to use L1 as initial stack */ 121 #define CONFIG_L1_INIT_RAM 122 #define CONFIG_SYS_INIT_RAM_LOCK 123 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 124 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 125 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 126 /* The assembler doesn't like typecast */ 127 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 128 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 129 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 130 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 131 132 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 133 GENERATED_GBL_DATA_SIZE) 134 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 135 136 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 137 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 138 139 /* Serial Port - controlled on board with jumper J8 140 * open - index 2 141 * shorted - index 1 142 */ 143 #define CONFIG_CONS_INDEX 1 144 #define CONFIG_SYS_NS16550_SERIAL 145 #define CONFIG_SYS_NS16550_REG_SIZE 1 146 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 147 148 #define CONFIG_SYS_BAUDRATE_TABLE \ 149 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 150 151 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 152 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 153 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 154 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 155 156 /* Use the HUSH parser */ 157 #define CONFIG_SYS_HUSH_PARSER 158 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 159 160 /* pass open firmware flat tree */ 161 #define CONFIG_OF_LIBFDT 162 #define CONFIG_OF_BOARD_SETUP 163 #define CONFIG_OF_STDOUT_VIA_ALIAS 164 165 /* new uImage format support */ 166 #define CONFIG_FIT 167 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 168 169 /* I2C */ 170 #define CONFIG_SYS_I2C 171 #define CONFIG_SYS_I2C_FSL 172 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 173 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 174 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 175 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 176 177 /* 178 * RapidIO 179 */ 180 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 181 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 182 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 183 184 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 185 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 186 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 187 188 /* 189 * General PCI 190 * Memory space is mapped 1-1, but I/O space must start from 0. 191 */ 192 193 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 194 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 195 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 196 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 197 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 198 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 199 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 200 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 201 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 202 203 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 204 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 205 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 206 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 207 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 208 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 209 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 210 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 211 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 212 213 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 214 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 215 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 216 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 217 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 218 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 219 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 220 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 221 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 222 223 /* controller 4, Base address 203000 */ 224 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 225 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 226 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 227 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 228 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 229 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 230 231 #ifdef CONFIG_PCI 232 #define CONFIG_PCI_INDIRECT_BRIDGE 233 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 234 235 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 236 #define CONFIG_DOS_PARTITION 237 #endif /* CONFIG_PCI */ 238 239 /* SATA */ 240 #ifdef CONFIG_FSL_SATA_V2 241 #define CONFIG_LIBATA 242 #define CONFIG_FSL_SATA 243 244 #define CONFIG_SYS_SATA_MAX_DEVICE 2 245 #define CONFIG_SATA1 246 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 247 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 248 #define CONFIG_SATA2 249 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 250 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 251 252 #define CONFIG_LBA48 253 #define CONFIG_CMD_SATA 254 #define CONFIG_DOS_PARTITION 255 #define CONFIG_CMD_EXT2 256 #endif 257 258 #ifdef CONFIG_FMAN_ENET 259 #define CONFIG_MII /* MII PHY management */ 260 #define CONFIG_ETHPRIME "FM1@DTSEC1" 261 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 262 #endif 263 264 /* 265 * Environment 266 */ 267 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 268 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 269 270 /* 271 * Command line configuration. 272 */ 273 #define CONFIG_CMD_DHCP 274 #define CONFIG_CMD_ERRATA 275 #define CONFIG_CMD_GREPENV 276 #define CONFIG_CMD_IRQ 277 #define CONFIG_CMD_I2C 278 #define CONFIG_CMD_MII 279 #define CONFIG_CMD_PING 280 281 #ifdef CONFIG_PCI 282 #define CONFIG_CMD_PCI 283 #endif 284 285 /* 286 * Miscellaneous configurable options 287 */ 288 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 289 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 290 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 291 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 292 #ifdef CONFIG_CMD_KGDB 293 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 294 #else 295 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 296 #endif 297 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 298 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 299 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 300 301 /* 302 * For booting Linux, the board info and command line data 303 * have to be in the first 64 MB of memory, since this is 304 * the maximum mapped by the Linux kernel during initialization. 305 */ 306 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 307 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 308 309 #ifdef CONFIG_CMD_KGDB 310 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 311 #endif 312 313 /* 314 * Environment Configuration 315 */ 316 #define CONFIG_ROOTPATH "/opt/nfsroot" 317 #define CONFIG_BOOTFILE "uImage" 318 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 319 320 /* default location for tftp and bootm */ 321 #define CONFIG_LOADADDR 1000000 322 323 324 #define CONFIG_BAUDRATE 115200 325 326 #define CONFIG_HVBOOT \ 327 "setenv bootargs config-addr=0x60000000; " \ 328 "bootm 0x01000000 - 0x00f00000" 329 330 #endif /* __CONFIG_H */ 331