1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * Corenet DS style board configuration file 9 */ 10 #ifndef __T4QDS_H 11 #define __T4QDS_H 12 13 /* High Level Configuration Options */ 14 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 15 #define CONFIG_MP /* support multiple processors */ 16 17 #ifndef CONFIG_SYS_TEXT_BASE 18 #define CONFIG_SYS_TEXT_BASE 0xeff40000 19 #endif 20 21 #ifndef CONFIG_RESET_VECTOR_ADDRESS 22 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 23 #endif 24 25 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 26 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 27 #define CONFIG_PCIE1 /* PCIE controller 1 */ 28 #define CONFIG_PCIE2 /* PCIE controller 2 */ 29 #define CONFIG_PCIE3 /* PCIE controller 3 */ 30 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 31 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 32 33 #define CONFIG_SYS_SRIO 34 #define CONFIG_SRIO1 /* SRIO port 1 */ 35 #define CONFIG_SRIO2 /* SRIO port 2 */ 36 37 #define CONFIG_ENV_OVERWRITE 38 39 /* 40 * These can be toggled for performance analysis, otherwise use default. 41 */ 42 #define CONFIG_SYS_CACHE_STASHING 43 #define CONFIG_BTB /* toggle branch predition */ 44 #ifdef CONFIG_DDR_ECC 45 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 46 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 47 #endif 48 49 #define CONFIG_ENABLE_36BIT_PHYS 50 51 #define CONFIG_ADDR_MAP 52 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 53 54 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 55 #define CONFIG_SYS_MEMTEST_END 0x00400000 56 #define CONFIG_SYS_ALT_MEMTEST 57 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 58 59 /* 60 * Config the L3 Cache as L3 SRAM 61 */ 62 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 63 #define CONFIG_SYS_L3_SIZE (512 << 10) 64 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 65 #ifdef CONFIG_RAMBOOT_PBL 66 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 67 #endif 68 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 69 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 70 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 71 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 72 73 #define CONFIG_SYS_DCSRBAR 0xf0000000 74 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 75 76 /* 77 * DDR Setup 78 */ 79 #define CONFIG_VERY_BIG_RAM 80 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 81 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 82 83 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 84 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 85 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 86 87 #define CONFIG_DDR_SPD 88 89 /* 90 * IFC Definitions 91 */ 92 #define CONFIG_SYS_FLASH_BASE 0xe0000000 93 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 94 95 #ifdef CONFIG_SPL_BUILD 96 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 97 #else 98 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 99 #endif 100 101 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 102 #define CONFIG_MISC_INIT_R 103 104 #define CONFIG_HWCONFIG 105 106 /* define to use L1 as initial stack */ 107 #define CONFIG_L1_INIT_RAM 108 #define CONFIG_SYS_INIT_RAM_LOCK 109 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 110 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 111 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 112 /* The assembler doesn't like typecast */ 113 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 114 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 115 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 116 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 117 118 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 119 GENERATED_GBL_DATA_SIZE) 120 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 121 122 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 123 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 124 125 /* Serial Port - controlled on board with jumper J8 126 * open - index 2 127 * shorted - index 1 128 */ 129 #define CONFIG_CONS_INDEX 1 130 #define CONFIG_SYS_NS16550_SERIAL 131 #define CONFIG_SYS_NS16550_REG_SIZE 1 132 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 133 134 #define CONFIG_SYS_BAUDRATE_TABLE \ 135 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 136 137 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 138 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 139 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 140 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 141 142 /* I2C */ 143 #define CONFIG_SYS_I2C 144 #define CONFIG_SYS_I2C_FSL 145 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 146 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 147 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 148 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 149 150 /* 151 * RapidIO 152 */ 153 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 154 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 155 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 156 157 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 158 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 159 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 160 161 /* 162 * General PCI 163 * Memory space is mapped 1-1, but I/O space must start from 0. 164 */ 165 166 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 167 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 168 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 169 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 170 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 171 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 172 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 173 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 174 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 175 176 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 177 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 178 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 179 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 180 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 181 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 182 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 183 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 184 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 185 186 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 187 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 188 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 189 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 190 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 191 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 192 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 193 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 194 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 195 196 /* controller 4, Base address 203000 */ 197 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 198 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 199 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 200 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 201 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 202 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 203 204 #ifdef CONFIG_PCI 205 #define CONFIG_PCI_INDIRECT_BRIDGE 206 207 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 208 #endif /* CONFIG_PCI */ 209 210 /* SATA */ 211 #ifdef CONFIG_FSL_SATA_V2 212 #define CONFIG_LIBATA 213 #define CONFIG_FSL_SATA 214 215 #define CONFIG_SYS_SATA_MAX_DEVICE 2 216 #define CONFIG_SATA1 217 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 218 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 219 #define CONFIG_SATA2 220 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 221 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 222 223 #define CONFIG_LBA48 224 #endif 225 226 #ifdef CONFIG_FMAN_ENET 227 #define CONFIG_MII /* MII PHY management */ 228 #define CONFIG_ETHPRIME "FM1@DTSEC1" 229 #endif 230 231 /* 232 * Environment 233 */ 234 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 235 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 236 237 /* 238 * Command line configuration. 239 */ 240 241 /* 242 * Miscellaneous configurable options 243 */ 244 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 245 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 246 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 247 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 248 #ifdef CONFIG_CMD_KGDB 249 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 250 #else 251 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 252 #endif 253 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 254 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 255 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 256 257 /* 258 * For booting Linux, the board info and command line data 259 * have to be in the first 64 MB of memory, since this is 260 * the maximum mapped by the Linux kernel during initialization. 261 */ 262 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 263 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 264 265 #ifdef CONFIG_CMD_KGDB 266 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 267 #endif 268 269 /* 270 * Environment Configuration 271 */ 272 #define CONFIG_ROOTPATH "/opt/nfsroot" 273 #define CONFIG_BOOTFILE "uImage" 274 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 275 276 /* default location for tftp and bootm */ 277 #define CONFIG_LOADADDR 1000000 278 279 #define CONFIG_HVBOOT \ 280 "setenv bootargs config-addr=0x60000000; " \ 281 "bootm 0x01000000 - 0x00f00000" 282 283 #endif /* __CONFIG_H */ 284