1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * Corenet DS style board configuration file 25 */ 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 #ifdef CONFIG_RAMBOOT_PBL 30 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 31 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 32 #define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_pbi.cfg 33 #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t4qds/t4_rcw.cfg 34 #endif 35 36 #define CONFIG_CMD_REGINFO 37 38 /* High Level Configuration Options */ 39 #define CONFIG_BOOKE 40 #define CONFIG_E500 /* BOOKE e500 family */ 41 #define CONFIG_E500MC /* BOOKE e500mc family */ 42 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 43 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ 44 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 45 #define CONFIG_MP /* support multiple processors */ 46 47 #ifndef CONFIG_SYS_TEXT_BASE 48 #define CONFIG_SYS_TEXT_BASE 0xeff80000 49 #endif 50 51 #ifndef CONFIG_RESET_VECTOR_ADDRESS 52 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 53 #endif 54 55 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 56 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 57 #define CONFIG_FSL_IFC /* Enable IFC Support */ 58 #define CONFIG_PCI /* Enable PCI/PCIE */ 59 #define CONFIG_PCIE1 /* PCIE controler 1 */ 60 #define CONFIG_PCIE2 /* PCIE controler 2 */ 61 #define CONFIG_PCIE3 /* PCIE controler 3 */ 62 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 63 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 64 65 #define CONFIG_SYS_SRIO 66 #define CONFIG_SRIO1 /* SRIO port 1 */ 67 #define CONFIG_SRIO2 /* SRIO port 2 */ 68 69 #define CONFIG_FSL_LAW /* Use common FSL init code */ 70 71 #define CONFIG_ENV_OVERWRITE 72 73 #ifdef CONFIG_SYS_NO_FLASH 74 #define CONFIG_ENV_IS_NOWHERE 75 #else 76 #define CONFIG_FLASH_CFI_DRIVER 77 #define CONFIG_SYS_FLASH_CFI 78 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 79 #endif 80 81 #ifndef CONFIG_SYS_NO_FLASH 82 #if defined(CONFIG_SPIFLASH) 83 #define CONFIG_SYS_EXTRA_ENV_RELOC 84 #define CONFIG_ENV_IS_IN_SPI_FLASH 85 #define CONFIG_ENV_SPI_BUS 0 86 #define CONFIG_ENV_SPI_CS 0 87 #define CONFIG_ENV_SPI_MAX_HZ 10000000 88 #define CONFIG_ENV_SPI_MODE 0 89 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 90 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 91 #define CONFIG_ENV_SECT_SIZE 0x10000 92 #elif defined(CONFIG_SDCARD) 93 #define CONFIG_SYS_EXTRA_ENV_RELOC 94 #define CONFIG_ENV_IS_IN_MMC 95 #define CONFIG_SYS_MMC_ENV_DEV 0 96 #define CONFIG_ENV_SIZE 0x2000 97 #define CONFIG_ENV_OFFSET (512 * 1097) 98 #elif defined(CONFIG_NAND) 99 #define CONFIG_SYS_EXTRA_ENV_RELOC 100 #define CONFIG_ENV_IS_IN_NAND 101 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 102 #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 103 #else 104 #define CONFIG_ENV_IS_IN_FLASH 105 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 106 #define CONFIG_ENV_SIZE 0x2000 107 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 108 #endif 109 #else /* CONFIG_SYS_NO_FLASH */ 110 #define CONFIG_ENV_SIZE 0x2000 111 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 112 #endif 113 114 115 116 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 117 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 118 119 #ifndef __ASSEMBLY__ 120 unsigned long get_board_sys_clk(void); 121 unsigned long get_board_ddr_clk(void); 122 #endif 123 124 /* 125 * These can be toggled for performance analysis, otherwise use default. 126 */ 127 #define CONFIG_SYS_CACHE_STASHING 128 #define CONFIG_BTB /* toggle branch predition */ 129 #define CONFIG_DDR_ECC 130 #ifdef CONFIG_DDR_ECC 131 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 132 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 133 #endif 134 135 #define CONFIG_ENABLE_36BIT_PHYS 136 137 #ifdef CONFIG_PHYS_64BIT 138 #define CONFIG_ADDR_MAP 139 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 140 #endif 141 142 #if 0 143 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 144 #endif 145 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 146 #define CONFIG_SYS_MEMTEST_END 0x00400000 147 #define CONFIG_SYS_ALT_MEMTEST 148 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 149 150 /* 151 * Config the L3 Cache as L3 SRAM 152 */ 153 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 154 155 #ifdef CONFIG_PHYS_64BIT 156 #define CONFIG_SYS_DCSRBAR 0xf0000000 157 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 158 #endif 159 160 /* EEPROM */ 161 #define CONFIG_ID_EEPROM 162 #define CONFIG_SYS_I2C_EEPROM_NXID 163 #define CONFIG_SYS_EEPROM_BUS_NUM 0 164 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 165 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 166 167 /* 168 * DDR Setup 169 */ 170 #define CONFIG_VERY_BIG_RAM 171 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 172 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 173 174 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 175 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 176 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 177 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 178 179 #define CONFIG_DDR_SPD 180 #define CONFIG_FSL_DDR3 181 182 #define CONFIG_SYS_SPD_BUS_NUM 0 183 #define SPD_EEPROM_ADDRESS1 0x51 184 #define SPD_EEPROM_ADDRESS2 0x52 185 #define SPD_EEPROM_ADDRESS3 0x53 186 #define SPD_EEPROM_ADDRESS4 0x54 187 #define SPD_EEPROM_ADDRESS5 0x55 188 #define SPD_EEPROM_ADDRESS6 0x56 189 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 190 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 191 192 /* 193 * IFC Definitions 194 */ 195 #define CONFIG_SYS_FLASH_BASE 0xe0000000 196 #ifdef CONFIG_PHYS_64BIT 197 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 198 #else 199 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 200 #endif 201 202 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 203 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 204 + 0x8000000) | \ 205 CSPR_PORT_SIZE_16 | \ 206 CSPR_MSEL_NOR | \ 207 CSPR_V) 208 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 209 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 210 CSPR_PORT_SIZE_16 | \ 211 CSPR_MSEL_NOR | \ 212 CSPR_V) 213 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 214 /* NOR Flash Timing Params */ 215 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 216 217 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 218 FTIM0_NOR_TEADC(0x5) | \ 219 FTIM0_NOR_TEAHC(0x5)) 220 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 221 FTIM1_NOR_TRAD_NOR(0x1A) |\ 222 FTIM1_NOR_TSEQRAD_NOR(0x13)) 223 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 224 FTIM2_NOR_TCH(0x4) | \ 225 FTIM2_NOR_TWPH(0x0E) | \ 226 FTIM2_NOR_TWP(0x1c)) 227 #define CONFIG_SYS_NOR_FTIM3 0x0 228 229 #define CONFIG_SYS_FLASH_QUIET_TEST 230 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 231 232 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 233 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 234 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 235 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 236 237 #define CONFIG_SYS_FLASH_EMPTY_INFO 238 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 239 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 240 241 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 242 #define QIXIS_BASE 0xffdf0000 243 #define QIXIS_LBMAP_SWITCH 6 244 #define QIXIS_LBMAP_MASK 0x0f 245 #define QIXIS_LBMAP_SHIFT 0 246 #define QIXIS_LBMAP_DFLTBANK 0x00 247 #define QIXIS_LBMAP_ALTBANK 0x04 248 #define QIXIS_RST_CTL_RESET 0x83 249 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 250 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 251 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 252 #ifdef CONFIG_PHYS_64BIT 253 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 254 #else 255 #define QIXIS_BASE_PHYS QIXIS_BASE 256 #endif 257 258 #define CONFIG_SYS_CSPR3_EXT (0xf) 259 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 260 | CSPR_PORT_SIZE_8 \ 261 | CSPR_MSEL_GPCM \ 262 | CSPR_V) 263 #define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024) 264 #define CONFIG_SYS_CSOR3 0x0 265 /* QIXIS Timing parameters for IFC CS3 */ 266 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 267 FTIM0_GPCM_TEADC(0x0e) | \ 268 FTIM0_GPCM_TEAHC(0x0e)) 269 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 270 FTIM1_GPCM_TRAD(0x3f)) 271 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 272 FTIM2_GPCM_TCH(0x0) | \ 273 FTIM2_GPCM_TWP(0x1f)) 274 #define CONFIG_SYS_CS3_FTIM3 0x0 275 276 /* NAND Flash on IFC */ 277 #define CONFIG_NAND_FSL_IFC 278 #define CONFIG_SYS_NAND_BASE 0xff800000 279 #ifdef CONFIG_PHYS_64BIT 280 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 281 #else 282 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 283 #endif 284 285 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 286 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 287 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 288 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 289 | CSPR_V) 290 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 291 292 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 293 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 294 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 295 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 296 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 297 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 298 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 299 300 #define CONFIG_SYS_NAND_ONFI_DETECTION 301 302 /* ONFI NAND Flash mode0 Timing Params */ 303 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 304 FTIM0_NAND_TWP(0x18) | \ 305 FTIM0_NAND_TWCHT(0x07) | \ 306 FTIM0_NAND_TWH(0x0a)) 307 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 308 FTIM1_NAND_TWBE(0x39) | \ 309 FTIM1_NAND_TRR(0x0e) | \ 310 FTIM1_NAND_TRP(0x18)) 311 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 312 FTIM2_NAND_TREH(0x0a) | \ 313 FTIM2_NAND_TWHRE(0x1e)) 314 #define CONFIG_SYS_NAND_FTIM3 0x0 315 316 #define CONFIG_SYS_NAND_DDR_LAW 11 317 318 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 319 #define CONFIG_SYS_MAX_NAND_DEVICE 1 320 #define CONFIG_MTD_NAND_VERIFY_WRITE 321 #define CONFIG_CMD_NAND 322 323 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 324 325 #if defined(CONFIG_NAND) 326 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 327 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 328 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 329 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 330 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 331 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 332 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 333 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 334 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 335 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 336 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 337 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 338 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 339 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 340 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 341 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 342 #else 343 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 344 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 345 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 346 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 347 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 348 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 349 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 350 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 351 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 352 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 353 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 354 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 355 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 356 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 357 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 358 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 359 #endif 360 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 361 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 362 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 363 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 364 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 365 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 366 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 367 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 368 369 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 370 371 #if defined(CONFIG_RAMBOOT_PBL) 372 #define CONFIG_SYS_RAMBOOT 373 #endif 374 375 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 376 #define CONFIG_MISC_INIT_R 377 378 #define CONFIG_HWCONFIG 379 380 /* define to use L1 as initial stack */ 381 #define CONFIG_L1_INIT_RAM 382 #define CONFIG_SYS_INIT_RAM_LOCK 383 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 384 #ifdef CONFIG_PHYS_64BIT 385 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 386 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 387 /* The assembler doesn't like typecast */ 388 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 389 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 390 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 391 #else 392 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */ 393 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 394 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 395 #endif 396 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 397 398 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 399 GENERATED_GBL_DATA_SIZE) 400 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 401 402 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 403 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 404 405 /* Serial Port - controlled on board with jumper J8 406 * open - index 2 407 * shorted - index 1 408 */ 409 #define CONFIG_CONS_INDEX 1 410 #define CONFIG_SYS_NS16550 411 #define CONFIG_SYS_NS16550_SERIAL 412 #define CONFIG_SYS_NS16550_REG_SIZE 1 413 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 414 415 #define CONFIG_SYS_BAUDRATE_TABLE \ 416 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 417 418 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 419 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 420 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 421 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 422 423 /* Use the HUSH parser */ 424 #define CONFIG_SYS_HUSH_PARSER 425 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 426 427 /* pass open firmware flat tree */ 428 #define CONFIG_OF_LIBFDT 429 #define CONFIG_OF_BOARD_SETUP 430 #define CONFIG_OF_STDOUT_VIA_ALIAS 431 432 /* new uImage format support */ 433 #define CONFIG_FIT 434 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 435 436 /* I2C */ 437 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 438 #define CONFIG_HARD_I2C /* I2C with hardware support */ 439 #define CONFIG_I2C_MULTI_BUS 440 #define CONFIG_I2C_CMD_TREE 441 #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ 442 #define CONFIG_SYS_I2C_SLAVE 0x7F 443 #define CONFIG_SYS_I2C_OFFSET 0x118000 444 #define CONFIG_SYS_I2C2_OFFSET 0x118100 445 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 446 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 447 448 #define I2C_MUX_CH_DEFAULT 0x8 449 #define I2C_MUX_CH_VOL_MONITOR 0xa 450 #define I2C_MUX_CH_VSC3316_FS 0xc 451 #define I2C_MUX_CH_VSC3316_BS 0xd 452 453 /* Voltage monitor on channel 2*/ 454 #define I2C_VOL_MONITOR_ADDR 0x40 455 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 456 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 457 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 458 459 /* VSC Crossbar switches */ 460 #define CONFIG_VSC_CROSSBAR 461 #define VSC3316_FSM_TX_ADDR 0x70 462 #define VSC3316_FSM_RX_ADDR 0x71 463 464 /* 465 * RapidIO 466 */ 467 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 468 #ifdef CONFIG_PHYS_64BIT 469 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 470 #else 471 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 472 #endif 473 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 474 475 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 476 #ifdef CONFIG_PHYS_64BIT 477 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 478 #else 479 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 480 #endif 481 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 482 483 /* 484 * for slave u-boot IMAGE instored in master memory space, 485 * PHYS must be aligned based on the SIZE 486 */ 487 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull 488 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull 489 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ 490 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull 491 /* 492 * for slave UCODE and ENV instored in master memory space, 493 * PHYS must be aligned based on the SIZE 494 */ 495 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull 496 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 497 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 498 499 /* slave core release by master*/ 500 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 501 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 502 503 /* 504 * SRIO_PCIE_BOOT - SLAVE 505 */ 506 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 507 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 508 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 509 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 510 #endif 511 /* 512 * eSPI - Enhanced SPI 513 */ 514 #define CONFIG_FSL_ESPI 515 #define CONFIG_SPI_FLASH 516 #define CONFIG_SPI_FLASH_SST 517 #define CONFIG_CMD_SF 518 #define CONFIG_SF_DEFAULT_SPEED 10000000 519 #define CONFIG_SF_DEFAULT_MODE 0 520 521 /* 522 * General PCI 523 * Memory space is mapped 1-1, but I/O space must start from 0. 524 */ 525 526 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 527 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 528 #ifdef CONFIG_PHYS_64BIT 529 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 530 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 531 #else 532 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 533 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 534 #endif 535 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 536 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 537 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 538 #ifdef CONFIG_PHYS_64BIT 539 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 540 #else 541 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 542 #endif 543 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 544 545 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 546 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 547 #ifdef CONFIG_PHYS_64BIT 548 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 549 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 550 #else 551 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 552 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 553 #endif 554 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 555 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 556 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 557 #ifdef CONFIG_PHYS_64BIT 558 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 559 #else 560 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 561 #endif 562 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 563 564 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 565 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 566 #ifdef CONFIG_PHYS_64BIT 567 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 568 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 569 #else 570 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 571 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 572 #endif 573 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 574 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 575 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 576 #ifdef CONFIG_PHYS_64BIT 577 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 578 #else 579 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 580 #endif 581 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 582 583 /* controller 4, Base address 203000 */ 584 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 585 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 586 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 587 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 588 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 589 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 590 591 /* Qman/Bman */ 592 #ifndef CONFIG_NOBQFMAN 593 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 594 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 595 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 596 #ifdef CONFIG_PHYS_64BIT 597 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 598 #else 599 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 600 #endif 601 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 602 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 603 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 604 #ifdef CONFIG_PHYS_64BIT 605 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 606 #else 607 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 608 #endif 609 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 610 611 #define CONFIG_SYS_DPAA_FMAN 612 #define CONFIG_SYS_DPAA_PME 613 #define CONFIG_SYS_PMAN 614 #define CONFIG_SYS_DPAA_DCE 615 #define CONFIG_SYS_INTERLAKEN 616 617 /* Default address of microcode for the Linux Fman driver */ 618 #if defined(CONFIG_SPIFLASH) 619 /* 620 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 621 * env, so we got 0x110000. 622 */ 623 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 624 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 625 #elif defined(CONFIG_SDCARD) 626 /* 627 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 628 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 629 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 630 */ 631 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 632 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) 633 #elif defined(CONFIG_NAND) 634 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 635 #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) 636 #else 637 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 638 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 639 #endif 640 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 641 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 642 #endif /* CONFIG_NOBQFMAN */ 643 644 #ifdef CONFIG_SYS_DPAA_FMAN 645 #define CONFIG_FMAN_ENET 646 #define CONFIG_PHYLIB_10G 647 #define CONFIG_PHY_VITESSE 648 #define CONFIG_PHY_TERANETICS 649 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 650 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 651 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 652 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 653 #define FM1_10GEC1_PHY_ADDR 0x0 654 #define FM1_10GEC2_PHY_ADDR 0x1 655 #define FM2_10GEC1_PHY_ADDR 0x2 656 #define FM2_10GEC2_PHY_ADDR 0x3 657 #endif 658 659 #ifdef CONFIG_PCI 660 #define CONFIG_NET_MULTI 661 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 662 #define CONFIG_E1000 663 664 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 665 #define CONFIG_DOS_PARTITION 666 #endif /* CONFIG_PCI */ 667 668 /* SATA */ 669 #ifdef CONFIG_FSL_SATA_V2 670 #define CONFIG_LIBATA 671 #define CONFIG_FSL_SATA 672 673 #define CONFIG_SYS_SATA_MAX_DEVICE 2 674 #define CONFIG_SATA1 675 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 676 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 677 #define CONFIG_SATA2 678 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 679 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 680 681 #define CONFIG_LBA48 682 #define CONFIG_CMD_SATA 683 #define CONFIG_DOS_PARTITION 684 #define CONFIG_CMD_EXT2 685 #endif 686 687 #ifdef CONFIG_FMAN_ENET 688 #define CONFIG_MII /* MII PHY management */ 689 #define CONFIG_ETHPRIME "FM1@DTSEC1" 690 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 691 #endif 692 693 /* 694 * Environment 695 */ 696 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 697 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 698 699 /* 700 * Command line configuration. 701 */ 702 #include <config_cmd_default.h> 703 704 #define CONFIG_CMD_DHCP 705 #define CONFIG_CMD_ELF 706 #define CONFIG_CMD_ERRATA 707 #define CONFIG_CMD_GREPENV 708 #define CONFIG_CMD_IRQ 709 #define CONFIG_CMD_I2C 710 #define CONFIG_CMD_MII 711 #define CONFIG_CMD_PING 712 #define CONFIG_CMD_SETEXPR 713 714 #ifdef CONFIG_PCI 715 #define CONFIG_CMD_PCI 716 #define CONFIG_CMD_NET 717 #endif 718 719 /* 720 * USB 721 */ 722 #define CONFIG_CMD_USB 723 #define CONFIG_USB_STORAGE 724 #define CONFIG_USB_EHCI 725 #define CONFIG_USB_EHCI_FSL 726 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 727 #define CONFIG_CMD_EXT2 728 #define CONFIG_HAS_FSL_DR_USB 729 730 #define CONFIG_MMC 731 732 #ifdef CONFIG_MMC 733 #define CONFIG_FSL_ESDHC 734 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 735 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 736 #define CONFIG_CMD_MMC 737 #define CONFIG_GENERIC_MMC 738 #define CONFIG_CMD_EXT2 739 #define CONFIG_CMD_FAT 740 #define CONFIG_DOS_PARTITION 741 #endif 742 743 /* 744 * Miscellaneous configurable options 745 */ 746 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 747 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 748 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 749 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 750 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 751 #ifdef CONFIG_CMD_KGDB 752 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 753 #else 754 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 755 #endif 756 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 757 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 758 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 759 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ 760 761 /* 762 * For booting Linux, the board info and command line data 763 * have to be in the first 64 MB of memory, since this is 764 * the maximum mapped by the Linux kernel during initialization. 765 */ 766 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 767 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 768 769 #ifdef CONFIG_CMD_KGDB 770 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 771 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 772 #endif 773 774 /* 775 * Environment Configuration 776 */ 777 #define CONFIG_ROOTPATH "/opt/nfsroot" 778 #define CONFIG_BOOTFILE "uImage" 779 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 780 781 /* default location for tftp and bootm */ 782 #define CONFIG_LOADADDR 1000000 783 784 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 785 786 #define CONFIG_BAUDRATE 115200 787 788 #define __USB_PHY_TYPE utmi 789 790 /* 791 * T4240 has 3 DDR controllers. Default to 3way_4KB interleaving. It can be 792 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 793 * cacheline interleaving. It can be cacheline, page, bank, superbank. 794 * See doc/README.fsl-ddr for details. 795 */ 796 #ifdef CONFIG_PPC_T4240 797 #define CTRL_INTLV_PREFERED 3way_4KB 798 #else 799 #define CTRL_INTLV_PREFERED cacheline 800 #endif 801 802 #define CONFIG_EXTRA_ENV_SETTINGS \ 803 "hwconfig=fsl_ddr:" \ 804 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 805 "bank_intlv=auto;" \ 806 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 807 "netdev=eth0\0" \ 808 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 809 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 810 "tftpflash=tftpboot $loadaddr $uboot && " \ 811 "protect off $ubootaddr +$filesize && " \ 812 "erase $ubootaddr +$filesize && " \ 813 "cp.b $loadaddr $ubootaddr $filesize && " \ 814 "protect on $ubootaddr +$filesize && " \ 815 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 816 "consoledev=ttyS0\0" \ 817 "ramdiskaddr=2000000\0" \ 818 "ramdiskfile=t4240qds/ramdisk.uboot\0" \ 819 "fdtaddr=c00000\0" \ 820 "fdtfile=t4240qds/t4240qds.dtb\0" \ 821 "bdev=sda3\0" \ 822 "c=ffe\0" 823 824 /* For emulation this causes u-boot to jump to the start of the proof point 825 app code automatically */ 826 #define CONFIG_PROOF_POINTS \ 827 "setenv bootargs root=/dev/$bdev rw " \ 828 "console=$consoledev,$baudrate $othbootargs;" \ 829 "cpu 1 release 0x29000000 - - -;" \ 830 "cpu 2 release 0x29000000 - - -;" \ 831 "cpu 3 release 0x29000000 - - -;" \ 832 "cpu 4 release 0x29000000 - - -;" \ 833 "cpu 5 release 0x29000000 - - -;" \ 834 "cpu 6 release 0x29000000 - - -;" \ 835 "cpu 7 release 0x29000000 - - -;" \ 836 "go 0x29000000" 837 838 #define CONFIG_HVBOOT \ 839 "setenv bootargs config-addr=0x60000000; " \ 840 "bootm 0x01000000 - 0x00f00000" 841 842 #define CONFIG_ALU \ 843 "setenv bootargs root=/dev/$bdev rw " \ 844 "console=$consoledev,$baudrate $othbootargs;" \ 845 "cpu 1 release 0x01000000 - - -;" \ 846 "cpu 2 release 0x01000000 - - -;" \ 847 "cpu 3 release 0x01000000 - - -;" \ 848 "cpu 4 release 0x01000000 - - -;" \ 849 "cpu 5 release 0x01000000 - - -;" \ 850 "cpu 6 release 0x01000000 - - -;" \ 851 "cpu 7 release 0x01000000 - - -;" \ 852 "go 0x01000000" 853 854 #define CONFIG_LINUX \ 855 "setenv bootargs root=/dev/ram rw " \ 856 "console=$consoledev,$baudrate $othbootargs;" \ 857 "setenv ramdiskaddr 0x02000000;" \ 858 "setenv fdtaddr 0x00c00000;" \ 859 "setenv loadaddr 0x1000000;" \ 860 "bootm $loadaddr $ramdiskaddr $fdtaddr" 861 862 #define CONFIG_HDBOOT \ 863 "setenv bootargs root=/dev/$bdev rw " \ 864 "console=$consoledev,$baudrate $othbootargs;" \ 865 "tftp $loadaddr $bootfile;" \ 866 "tftp $fdtaddr $fdtfile;" \ 867 "bootm $loadaddr - $fdtaddr" 868 869 #define CONFIG_NFSBOOTCOMMAND \ 870 "setenv bootargs root=/dev/nfs rw " \ 871 "nfsroot=$serverip:$rootpath " \ 872 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 873 "console=$consoledev,$baudrate $othbootargs;" \ 874 "tftp $loadaddr $bootfile;" \ 875 "tftp $fdtaddr $fdtfile;" \ 876 "bootm $loadaddr - $fdtaddr" 877 878 #define CONFIG_RAMBOOTCOMMAND \ 879 "setenv bootargs root=/dev/ram rw " \ 880 "console=$consoledev,$baudrate $othbootargs;" \ 881 "tftp $ramdiskaddr $ramdiskfile;" \ 882 "tftp $loadaddr $bootfile;" \ 883 "tftp $fdtaddr $fdtfile;" \ 884 "bootm $loadaddr $ramdiskaddr $fdtaddr" 885 886 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 887 888 #ifdef CONFIG_SECURE_BOOT 889 #include <asm/fsl_secure_boot.h> 890 #endif 891 892 #endif /* __CONFIG_H */ 893