1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * Corenet DS style board configuration file 9 */ 10 #ifndef __T4QDS_H 11 #define __T4QDS_H 12 13 #define CONFIG_CMD_REGINFO 14 15 /* High Level Configuration Options */ 16 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 17 #define CONFIG_MP /* support multiple processors */ 18 19 #ifndef CONFIG_SYS_TEXT_BASE 20 #define CONFIG_SYS_TEXT_BASE 0xeff40000 21 #endif 22 23 #ifndef CONFIG_RESET_VECTOR_ADDRESS 24 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 25 #endif 26 27 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 28 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 29 #define CONFIG_FSL_IFC /* Enable IFC Support */ 30 #define CONFIG_PCIE1 /* PCIE controller 1 */ 31 #define CONFIG_PCIE2 /* PCIE controller 2 */ 32 #define CONFIG_PCIE3 /* PCIE controller 3 */ 33 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 34 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 35 36 #define CONFIG_SYS_SRIO 37 #define CONFIG_SRIO1 /* SRIO port 1 */ 38 #define CONFIG_SRIO2 /* SRIO port 2 */ 39 40 #define CONFIG_ENV_OVERWRITE 41 42 /* 43 * These can be toggled for performance analysis, otherwise use default. 44 */ 45 #define CONFIG_SYS_CACHE_STASHING 46 #define CONFIG_BTB /* toggle branch predition */ 47 #ifdef CONFIG_DDR_ECC 48 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 49 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 50 #endif 51 52 #define CONFIG_ENABLE_36BIT_PHYS 53 54 #define CONFIG_ADDR_MAP 55 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 56 57 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 58 #define CONFIG_SYS_MEMTEST_END 0x00400000 59 #define CONFIG_SYS_ALT_MEMTEST 60 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 61 62 /* 63 * Config the L3 Cache as L3 SRAM 64 */ 65 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 66 #define CONFIG_SYS_L3_SIZE (512 << 10) 67 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 68 #ifdef CONFIG_RAMBOOT_PBL 69 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 70 #endif 71 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 72 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 73 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 74 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 75 76 #define CONFIG_SYS_DCSRBAR 0xf0000000 77 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 78 79 /* 80 * DDR Setup 81 */ 82 #define CONFIG_VERY_BIG_RAM 83 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 84 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 85 86 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 87 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 88 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 89 90 #define CONFIG_DDR_SPD 91 92 /* 93 * IFC Definitions 94 */ 95 #define CONFIG_SYS_FLASH_BASE 0xe0000000 96 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 97 98 #ifdef CONFIG_SPL_BUILD 99 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 100 #else 101 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 102 #endif 103 104 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 105 #define CONFIG_MISC_INIT_R 106 107 #define CONFIG_HWCONFIG 108 109 /* define to use L1 as initial stack */ 110 #define CONFIG_L1_INIT_RAM 111 #define CONFIG_SYS_INIT_RAM_LOCK 112 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 113 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 114 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 115 /* The assembler doesn't like typecast */ 116 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 117 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 118 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 119 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 120 121 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 122 GENERATED_GBL_DATA_SIZE) 123 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 124 125 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 126 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 127 128 /* Serial Port - controlled on board with jumper J8 129 * open - index 2 130 * shorted - index 1 131 */ 132 #define CONFIG_CONS_INDEX 1 133 #define CONFIG_SYS_NS16550_SERIAL 134 #define CONFIG_SYS_NS16550_REG_SIZE 1 135 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 136 137 #define CONFIG_SYS_BAUDRATE_TABLE \ 138 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 139 140 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 141 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 142 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 143 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 144 145 /* I2C */ 146 #define CONFIG_SYS_I2C 147 #define CONFIG_SYS_I2C_FSL 148 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 149 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 150 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 151 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 152 153 /* 154 * RapidIO 155 */ 156 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 157 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 158 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 159 160 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 161 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 162 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 163 164 /* 165 * General PCI 166 * Memory space is mapped 1-1, but I/O space must start from 0. 167 */ 168 169 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 170 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 171 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 172 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 173 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 174 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 175 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 176 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 177 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 178 179 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 180 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 181 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 182 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 183 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 184 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 185 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 186 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 187 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 188 189 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 190 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 191 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 192 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 193 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 194 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 195 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 196 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 197 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 198 199 /* controller 4, Base address 203000 */ 200 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 201 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 202 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 203 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 204 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 205 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 206 207 #ifdef CONFIG_PCI 208 #define CONFIG_PCI_INDIRECT_BRIDGE 209 210 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 211 #define CONFIG_DOS_PARTITION 212 #endif /* CONFIG_PCI */ 213 214 /* SATA */ 215 #ifdef CONFIG_FSL_SATA_V2 216 #define CONFIG_LIBATA 217 #define CONFIG_FSL_SATA 218 219 #define CONFIG_SYS_SATA_MAX_DEVICE 2 220 #define CONFIG_SATA1 221 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 222 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 223 #define CONFIG_SATA2 224 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 225 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 226 227 #define CONFIG_LBA48 228 #define CONFIG_CMD_SATA 229 #define CONFIG_DOS_PARTITION 230 #endif 231 232 #ifdef CONFIG_FMAN_ENET 233 #define CONFIG_MII /* MII PHY management */ 234 #define CONFIG_ETHPRIME "FM1@DTSEC1" 235 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 236 #endif 237 238 /* 239 * Environment 240 */ 241 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 242 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 243 244 /* 245 * Command line configuration. 246 */ 247 #define CONFIG_CMD_ERRATA 248 #define CONFIG_CMD_IRQ 249 250 #ifdef CONFIG_PCI 251 #define CONFIG_CMD_PCI 252 #endif 253 254 /* 255 * Miscellaneous configurable options 256 */ 257 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 258 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 259 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 260 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 261 #ifdef CONFIG_CMD_KGDB 262 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 263 #else 264 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 265 #endif 266 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 267 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 268 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 269 270 /* 271 * For booting Linux, the board info and command line data 272 * have to be in the first 64 MB of memory, since this is 273 * the maximum mapped by the Linux kernel during initialization. 274 */ 275 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 276 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 277 278 #ifdef CONFIG_CMD_KGDB 279 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 280 #endif 281 282 /* 283 * Environment Configuration 284 */ 285 #define CONFIG_ROOTPATH "/opt/nfsroot" 286 #define CONFIG_BOOTFILE "uImage" 287 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 288 289 /* default location for tftp and bootm */ 290 #define CONFIG_LOADADDR 1000000 291 292 #define CONFIG_BAUDRATE 115200 293 294 #define CONFIG_HVBOOT \ 295 "setenv bootargs config-addr=0x60000000; " \ 296 "bootm 0x01000000 - 0x00f00000" 297 298 #endif /* __CONFIG_H */ 299