1 /* 2 * Copyright (C) 2006 Freescale Semiconductor, Inc. 3 * Dave Liu <daveliu@freescale.com> 4 * 5 * Copyright (C) 2007 Logic Product Development, Inc. 6 * Peter Barada <peterb@logicpd.com> 7 * 8 * Copyright (C) 2007 MontaVista Software, Inc. 9 * Anton Vorontsov <avorontsov@ru.mvista.com> 10 * 11 * (C) Copyright 2010 12 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 */ 16 17 #ifndef __CONFIG_H 18 #define __CONFIG_H 19 20 /* 21 * High Level Configuration Options 22 */ 23 24 /* This needs to be set prior to including km/km83xx-common.h */ 25 #define CONFIG_SYS_TEXT_BASE 0xF0000000 26 27 #if defined(CONFIG_SUVD3) /* SUVD3 board specific */ 28 #define CONFIG_HOSTNAME suvd3 29 #define CONFIG_KM_BOARD_NAME "suvd3" 30 /* include common defines/options for all 8321 Keymile boards */ 31 #include "km/km8321-common.h" 32 33 #elif defined(CONFIG_KMVECT1) /* VECT1 board specific */ 34 #define CONFIG_HOSTNAME kmvect1 35 #define CONFIG_KM_BOARD_NAME "kmvect1" 36 /* at end of uboot partition, before env */ 37 #define CONFIG_SYS_QE_FW_ADDR 0xF00B0000 38 /* include common defines/options for all 8309 Keymile boards */ 39 #include "km/km8309-common.h" 40 41 #elif defined(CONFIG_KMTEGR1) /* TEGR1 board specific */ 42 #define CONFIG_HOSTNAME kmtegr1 43 #define CONFIG_KM_BOARD_NAME "kmtegr1" 44 #define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" 45 #define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" 46 #define MTDIDS_DEFAULT "nor0=boot,nand0=app" 47 #define MTDPARTS_DEFAULT "mtdparts=" \ 48 "boot:" \ 49 "768k(u-boot)," \ 50 "256k(qe-fw)," \ 51 "128k(env)," \ 52 "128k(envred)," \ 53 "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");" \ 54 "app:" \ 55 "-(" CONFIG_KM_UBI_PARTITION_NAME_APP ");" 56 57 #define CONFIG_ENV_ADDR 0xF0100000 58 #define CONFIG_ENV_OFFSET 0x100000 59 60 #define CONFIG_NAND_ECC_BCH 61 #define CONFIG_NAND_KMETER1 62 #define CONFIG_SYS_MAX_NAND_DEVICE 1 63 #define NAND_MAX_CHIPS 1 64 65 /* include common defines/options for all 8309 Keymile boards */ 66 #include "km/km8309-common.h" 67 /* must be after the include because KMBEC_FPGA is otherwise undefined */ 68 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ 69 70 #else 71 #error Supported boards are: SUVD3, KMVECT1, KMTEGR1 72 #endif 73 74 #define CONFIG_SYS_APP1_BASE 0xA0000000 75 #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ 76 #define CONFIG_SYS_APP2_BASE 0xB0000000 77 #define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ 78 79 /* EEprom support */ 80 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 81 82 /* 83 * Init Local Bus Memory Controller: 84 * 85 * Bank Bus Machine PortSz Size Device 86 * ---- --- ------- ------ ----- ------ 87 * 2 Local UPMA 16 bit 256MB APP1 88 * 3 Local GPCM 16 bit 256MB APP2 89 * 90 */ 91 92 #if defined(CONFIG_SUVD3) || defined(CONFIG_KMVECT1) 93 /* 94 * APP1 on the local bus CS2 95 */ 96 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE 97 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) 98 99 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ 100 BR_PS_16 | \ 101 BR_MS_UPMA | \ 102 BR_V) 103 #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE)) 104 105 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ 106 BR_PS_16 | \ 107 BR_V) 108 109 #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ 110 OR_GPCM_CSNT | \ 111 OR_GPCM_ACS_DIV4 | \ 112 OR_GPCM_SCY_3 | \ 113 OR_GPCM_TRLX_SET) 114 115 #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 116 0x0000c000 | \ 117 MxMR_WLFx_2X) 118 119 #elif defined(CONFIG_KMTEGR1) 120 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ 121 BR_PS_16 | \ 122 BR_MS_GPCM | \ 123 BR_V) 124 125 #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ 126 OR_GPCM_SCY_5 | \ 127 OR_GPCM_TRLX_CLEAR | \ 128 OR_GPCM_EHTR_CLEAR) 129 130 #endif /* CONFIG_KMTEGR1 */ 131 132 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE 133 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) 134 135 /* 136 * MMU Setup 137 */ 138 #if defined(CONFIG_SUVD3) || defined(CONFIG_KMVECT1) 139 /* APP1: icache cacheable, but dcache-inhibit and guarded */ 140 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \ 141 BATL_MEMCOHERENCE) 142 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | BATU_BL_256M | \ 143 BATU_VS | BATU_VP) 144 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \ 145 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 146 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 147 148 #elif defined(CONFIG_KMTEGR1) 149 #define CONFIG_SYS_IBAT5L (0) 150 #define CONFIG_SYS_IBAT5U (0) 151 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 152 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 153 #endif /* CONFIG_KMTEGR1 */ 154 155 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \ 156 BATL_MEMCOHERENCE) 157 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \ 158 BATU_VS | BATU_VP) 159 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \ 160 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 161 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 162 163 /* 164 * QE UEC ethernet configuration 165 */ 166 #if defined(CONFIG_KMVECT1) 167 #define CONFIG_MV88E6352_SWITCH 168 #define CONFIG_KM_MVEXTSW_ADDR 0x10 169 170 /* ethernet port connected to simple switch 88e6122 (UEC0) */ 171 #define CONFIG_UEC_ETH1 172 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 173 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK9 174 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 175 176 #define CONFIG_FIXED_PHY 0xFFFFFFFF 177 #define CONFIG_SYS_FIXED_PHY_ADDR 0x1E /* unused address */ 178 #define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \ 179 {devnum, speed, duplex} 180 #define CONFIG_SYS_FIXED_PHY_PORTS \ 181 CONFIG_SYS_FIXED_PHY_PORT("UEC0", SPEED_100, DUPLEX_FULL) 182 183 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 184 #define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR 185 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII 186 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 187 #endif /* CONFIG_KMVECT1 */ 188 189 #if defined(CONFIG_KMVECT1) || defined(CONFIG_KMTEGR1) 190 /* ethernet port connected to piggy (UEC2) */ 191 #define CONFIG_HAS_ETH1 192 #define CONFIG_UEC_ETH2 193 #define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */ 194 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ 195 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK12 196 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH 197 #define CONFIG_SYS_UEC2_PHY_ADDR 0 198 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 199 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 200 #endif /* CONFIG_KMVECT1 || CONFIG_KMTEGR1 */ 201 202 #endif /* __CONFIG_H */ 203