1 /* 2 * Copyright (C) 2006 Freescale Semiconductor, Inc. 3 * Dave Liu <daveliu@freescale.com> 4 * 5 * Copyright (C) 2007 Logic Product Development, Inc. 6 * Peter Barada <peterb@logicpd.com> 7 * 8 * Copyright (C) 2007 MontaVista Software, Inc. 9 * Anton Vorontsov <avorontsov@ru.mvista.com> 10 * 11 * (C) Copyright 2010 12 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of 17 * the License, or (at your option) any later version. 18 */ 19 20 #ifndef __CONFIG_H 21 #define __CONFIG_H 22 23 /* 24 * High Level Configuration Options 25 */ 26 #define CONFIG_SUVD3 /* SUVD3 board specific */ 27 #define CONFIG_HOSTNAME suvd3 28 #define CONFIG_KM_BOARD_NAME "suvd3" 29 30 #define CONFIG_SYS_TEXT_BASE 0xF0000000 31 32 /* include common defines/options for all 8321 Keymile boards */ 33 #include "km/km8321-common.h" 34 35 #define CONFIG_SYS_APP1_BASE 0xA0000000 36 #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ 37 #define CONFIG_SYS_APP2_BASE 0xB0000000 38 #define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ 39 40 /* EEprom support */ 41 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 42 43 /* 44 * Init Local Bus Memory Controller: 45 * 46 * Bank Bus Machine PortSz Size Device 47 * ---- --- ------- ------ ----- ------ 48 * 2 Local UPMA 16 bit 256MB APP1 49 * 3 Local GPCM 16 bit 256MB APP2 50 * 51 */ 52 53 /* 54 * APP1 on the local bus CS2 55 */ 56 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE 57 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) 58 59 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ 60 BR_PS_16 | \ 61 BR_MS_UPMA | \ 62 BR_V) 63 #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE)) 64 65 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ 66 BR_PS_16 | \ 67 BR_V) 68 69 #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ 70 OR_GPCM_CSNT | \ 71 OR_GPCM_ACS_DIV4 | \ 72 OR_GPCM_SCY_3 | \ 73 OR_GPCM_TRLX_SET) 74 75 #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 76 0x0000c000 | \ 77 MxMR_WLFx_2X) 78 79 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE 80 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) 81 82 /* 83 * MMU Setup 84 */ 85 86 87 /* APP1: icache cacheable, but dcache-inhibit and guarded */ 88 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \ 89 BATL_MEMCOHERENCE) 90 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | BATU_BL_256M | \ 91 BATU_VS | BATU_VP) 92 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \ 93 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 94 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 95 96 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \ 97 BATL_MEMCOHERENCE) 98 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \ 99 BATU_VS | BATU_VP) 100 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \ 101 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 102 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 103 104 #endif /* __CONFIG_H */ 105