1 /* 2 * Copyright (C) 2006 Freescale Semiconductor, Inc. 3 * Dave Liu <daveliu@freescale.com> 4 * 5 * Copyright (C) 2007 Logic Product Development, Inc. 6 * Peter Barada <peterb@logicpd.com> 7 * 8 * Copyright (C) 2007 MontaVista Software, Inc. 9 * Anton Vorontsov <avorontsov@ru.mvista.com> 10 * 11 * (C) Copyright 2010 12 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 */ 16 17 #ifndef __CONFIG_H 18 #define __CONFIG_H 19 20 /* 21 * High Level Configuration Options 22 */ 23 24 /* This needs to be set prior to including km/km83xx-common.h */ 25 26 #if defined(CONFIG_SUVD3) /* SUVD3 board specific */ 27 #define CONFIG_HOSTNAME "suvd3" 28 #define CONFIG_KM_BOARD_NAME "suvd3" 29 /* include common defines/options for all 8321 Keymile boards */ 30 #include "km/km8321-common.h" 31 32 #elif defined(CONFIG_KMVECT1) /* VECT1 board specific */ 33 #define CONFIG_HOSTNAME "kmvect1" 34 #define CONFIG_KM_BOARD_NAME "kmvect1" 35 /* at end of uboot partition, before env */ 36 #define CONFIG_SYS_QE_FW_ADDR 0xF00B0000 37 /* include common defines/options for all 8309 Keymile boards */ 38 #include "km/km8309-common.h" 39 40 #elif defined(CONFIG_KMTEGR1) /* TEGR1 board specific */ 41 #define CONFIG_HOSTNAME "kmtegr1" 42 #define CONFIG_KM_BOARD_NAME "kmtegr1" 43 #define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" 44 #define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" 45 46 #define CONFIG_ENV_ADDR 0xF0100000 47 #define CONFIG_ENV_OFFSET 0x100000 48 49 #define CONFIG_NAND_ECC_BCH 50 #define CONFIG_NAND_KMETER1 51 #define CONFIG_SYS_MAX_NAND_DEVICE 1 52 #define NAND_MAX_CHIPS 1 53 54 /* include common defines/options for all 8309 Keymile boards */ 55 #include "km/km8309-common.h" 56 /* must be after the include because KMBEC_FPGA is otherwise undefined */ 57 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ 58 59 #else 60 #error Supported boards are: SUVD3, KMVECT1, KMTEGR1 61 #endif 62 63 #define CONFIG_SYS_APP1_BASE 0xA0000000 64 #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ 65 #define CONFIG_SYS_APP2_BASE 0xB0000000 66 #define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ 67 68 /* EEprom support */ 69 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 70 71 /* 72 * Init Local Bus Memory Controller: 73 * 74 * Bank Bus Machine PortSz Size Device 75 * ---- --- ------- ------ ----- ------ 76 * 2 Local UPMA 16 bit 256MB APP1 77 * 3 Local GPCM 16 bit 256MB APP2 78 * 79 */ 80 81 #if defined(CONFIG_SUVD3) || defined(CONFIG_KMVECT1) 82 /* 83 * APP1 on the local bus CS2 84 */ 85 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE 86 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) 87 88 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ 89 BR_PS_16 | \ 90 BR_MS_UPMA | \ 91 BR_V) 92 #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE)) 93 94 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ 95 BR_PS_16 | \ 96 BR_V) 97 98 #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ 99 OR_GPCM_CSNT | \ 100 OR_GPCM_ACS_DIV4 | \ 101 OR_GPCM_SCY_3 | \ 102 OR_GPCM_TRLX_SET) 103 104 #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 105 0x0000c000 | \ 106 MxMR_WLFx_2X) 107 108 #elif defined(CONFIG_KMTEGR1) 109 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ 110 BR_PS_16 | \ 111 BR_MS_GPCM | \ 112 BR_V) 113 114 #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ 115 OR_GPCM_SCY_5 | \ 116 OR_GPCM_TRLX_CLEAR | \ 117 OR_GPCM_EHTR_CLEAR) 118 119 #endif /* CONFIG_KMTEGR1 */ 120 121 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE 122 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) 123 124 /* 125 * MMU Setup 126 */ 127 #if defined(CONFIG_SUVD3) || defined(CONFIG_KMVECT1) 128 /* APP1: icache cacheable, but dcache-inhibit and guarded */ 129 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \ 130 BATL_MEMCOHERENCE) 131 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | BATU_BL_256M | \ 132 BATU_VS | BATU_VP) 133 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \ 134 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 135 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 136 137 #elif defined(CONFIG_KMTEGR1) 138 #define CONFIG_SYS_IBAT5L (0) 139 #define CONFIG_SYS_IBAT5U (0) 140 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 141 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 142 #endif /* CONFIG_KMTEGR1 */ 143 144 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \ 145 BATL_MEMCOHERENCE) 146 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \ 147 BATU_VS | BATU_VP) 148 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \ 149 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 150 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 151 152 /* 153 * QE UEC ethernet configuration 154 */ 155 #if defined(CONFIG_KMVECT1) 156 #define CONFIG_MV88E6352_SWITCH 157 #define CONFIG_KM_MVEXTSW_ADDR 0x10 158 159 /* ethernet port connected to simple switch 88e6122 (UEC0) */ 160 #define CONFIG_UEC_ETH1 161 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 162 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK9 163 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 164 165 #define CONFIG_FIXED_PHY 0xFFFFFFFF 166 #define CONFIG_SYS_FIXED_PHY_ADDR 0x1E /* unused address */ 167 #define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \ 168 {devnum, speed, duplex} 169 #define CONFIG_SYS_FIXED_PHY_PORTS \ 170 CONFIG_SYS_FIXED_PHY_PORT("UEC0", SPEED_100, DUPLEX_FULL) 171 172 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 173 #define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR 174 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII 175 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 176 #endif /* CONFIG_KMVECT1 */ 177 178 #if defined(CONFIG_KMVECT1) || defined(CONFIG_KMTEGR1) 179 /* ethernet port connected to piggy (UEC2) */ 180 #define CONFIG_HAS_ETH1 181 #define CONFIG_UEC_ETH2 182 #define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */ 183 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ 184 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK12 185 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH 186 #define CONFIG_SYS_UEC2_PHY_ADDR 0 187 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 188 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 189 #endif /* CONFIG_KMVECT1 || CONFIG_KMTEGR1 */ 190 191 #endif /* __CONFIG_H */ 192