xref: /openbmc/u-boot/include/configs/suvd3.h (revision 68fbc0e6)
1 /*
2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
3  *                    Dave Liu <daveliu@freescale.com>
4  *
5  * Copyright (C) 2007 Logic Product Development, Inc.
6  *                    Peter Barada <peterb@logicpd.com>
7  *
8  * Copyright (C) 2007 MontaVista Software, Inc.
9  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
10  *
11  * (C) Copyright 2010
12  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
13  *
14  * This program is free software; you can redistribute it and/or
15  * modify it under the terms of the GNU General Public License as
16  * published by the Free Software Foundation; either version 2 of
17  * the License, or (at your option) any later version.
18  */
19 
20 #ifndef __CONFIG_H
21 #define __CONFIG_H
22 
23 /*
24  * High Level Configuration Options
25  */
26 
27 /* This needs to be set prior to including km/km83xx-common.h */
28 #define	CONFIG_SYS_TEXT_BASE	0xF0000000
29 
30 #if defined(CONFIG_SUVD3)	/* SUVD3 board specific */
31 #define CONFIG_HOSTNAME		suvd3
32 #define CONFIG_KM_BOARD_NAME   "suvd3"
33 /* include common defines/options for all 8321 Keymile boards */
34 #include "km/km8321-common.h"
35 #elif defined(CONFIG_KMVECT1)   /* VECT1 board specific */
36 #define CONFIG_HOSTNAME		kmvect1
37 #define CONFIG_KM_BOARD_NAME   "kmvect1"
38 /* include common defines/options for all 8309 Keymile boards */
39 #include "km/km8309-common.h"
40 #else
41 #error Supported boards are: SUVD3, KMVECT1
42 #endif
43 
44 #define CONFIG_SYS_APP1_BASE		0xA0000000
45 #define CONFIG_SYS_APP1_SIZE		256 /* Megabytes */
46 #define CONFIG_SYS_APP2_BASE		0xB0000000
47 #define CONFIG_SYS_APP2_SIZE		256 /* Megabytes */
48 
49 /* EEprom support */
50 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
51 
52 /*
53  * Init Local Bus Memory Controller:
54  *
55  * Bank Bus     Machine PortSz  Size  Device
56  * ---- ---     ------- ------  -----  ------
57  *  2   Local   UPMA    16 bit  256MB APP1
58  *  3   Local   GPCM    16 bit  256MB APP2
59  *
60  */
61 
62 /*
63  * APP1 on the local bus CS2
64  */
65 #define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_APP1_BASE
66 #define CONFIG_SYS_LBLAWAR2_PRELIM	(LBLAWAR_EN | LBLAWAR_256MB)
67 
68 #define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_APP1_BASE | \
69 				 BR_PS_16 | \
70 				 BR_MS_UPMA | \
71 				 BR_V)
72 #define CONFIG_SYS_OR2_PRELIM	(MEG_TO_AM(CONFIG_SYS_APP1_SIZE))
73 
74 #define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_APP2_BASE | \
75 				 BR_PS_16 | \
76 				 BR_V)
77 
78 #define CONFIG_SYS_OR3_PRELIM	(MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
79 				 OR_GPCM_CSNT | \
80 				 OR_GPCM_ACS_DIV4 | \
81 				 OR_GPCM_SCY_3 | \
82 				 OR_GPCM_TRLX_SET)
83 
84 #define CONFIG_SYS_MAMR	(MxMR_GPL_x4DIS | \
85 			 0x0000c000 | \
86 			 MxMR_WLFx_2X)
87 
88 #define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_APP2_BASE
89 #define CONFIG_SYS_LBLAWAR3_PRELIM	(LBLAWAR_EN | LBLAWAR_256MB)
90 
91 /*
92  * MMU Setup
93  */
94 
95 
96 /* APP1:  icache cacheable, but dcache-inhibit and guarded */
97 #define CONFIG_SYS_IBAT5L	(CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
98 				 BATL_MEMCOHERENCE)
99 #define CONFIG_SYS_IBAT5U	(CONFIG_SYS_APP1_BASE | BATU_BL_256M | \
100 				 BATU_VS | BATU_VP)
101 #define CONFIG_SYS_DBAT5L	(CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
102 				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
103 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
104 
105 #define CONFIG_SYS_IBAT6L	(CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
106 				 BATL_MEMCOHERENCE)
107 #define CONFIG_SYS_IBAT6U	(CONFIG_SYS_APP2_BASE | BATU_BL_256M | \
108 				 BATU_VS | BATU_VP)
109 #define CONFIG_SYS_DBAT6L	(CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
110 				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
111 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
112 
113 /*
114  * QE UEC ethernet configuration
115  */
116 #if defined(CONFIG_KMVECT1)
117 #define CONFIG_MV88E6352_SWITCH
118 #define CONFIG_KM_MVEXTSW_ADDR		0x10
119 
120 /* ethernet port connected to simple switch 88e6122 (UEC0) */
121 #define CONFIG_UEC_ETH1
122 #define CONFIG_SYS_UEC1_UCC_NUM		0	/* UCC1 */
123 #define CONFIG_SYS_UEC1_RX_CLK		QE_CLK9
124 #define CONFIG_SYS_UEC1_TX_CLK		QE_CLK10
125 
126 #define CONFIG_FIXED_PHY		0xFFFFFFFF
127 #define CONFIG_SYS_FIXED_PHY_ADDR	0x1E	/* unused address */
128 #define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
129 		{devnum, speed, duplex}
130 #define CONFIG_SYS_FIXED_PHY_PORTS \
131 		CONFIG_SYS_FIXED_PHY_PORT("UEC0", SPEED_100, DUPLEX_FULL)
132 
133 #define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
134 #define CONFIG_SYS_UEC1_PHY_ADDR	CONFIG_SYS_FIXED_PHY_ADDR
135 #define CONFIG_SYS_UEC1_INTERFACE_TYPE	PHY_INTERFACE_MODE_MII
136 #define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
137 
138 /* ethernet port connected to piggy (UEC2) */
139 #define CONFIG_HAS_ETH1
140 #define CONFIG_UEC_ETH2
141 #define CONFIG_SYS_UEC2_UCC_NUM		2       /* UCC3 */
142 #define CONFIG_SYS_UEC2_RX_CLK		QE_CLK_NONE /* not used in RMII Mode */
143 #define CONFIG_SYS_UEC2_TX_CLK		QE_CLK12
144 #define CONFIG_SYS_UEC2_ETH_TYPE	FAST_ETH
145 #define CONFIG_SYS_UEC2_PHY_ADDR	0
146 #define CONFIG_SYS_UEC2_INTERFACE_TYPE	PHY_INTERFACE_MODE_RMII
147 #define CONFIG_SYS_UEC2_INTERFACE_SPEED	100
148 #endif /* CONFIG_KMVECT1 */
149 
150 #endif /* __CONFIG_H */
151