1 /* 2 * Copyright (C) 2006 Freescale Semiconductor, Inc. 3 * Dave Liu <daveliu@freescale.com> 4 * 5 * Copyright (C) 2007 Logic Product Development, Inc. 6 * Peter Barada <peterb@logicpd.com> 7 * 8 * Copyright (C) 2007 MontaVista Software, Inc. 9 * Anton Vorontsov <avorontsov@ru.mvista.com> 10 * 11 * (C) Copyright 2010 12 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of 17 * the License, or (at your option) any later version. 18 */ 19 20 #ifndef __CONFIG_H 21 #define __CONFIG_H 22 23 /* 24 * High Level Configuration Options 25 */ 26 #define CONFIG_QE /* Has QE */ 27 #define CONFIG_MPC832x /* MPC832x CPU specific */ 28 #define CONFIG_SUVD3 /* SUVD3 board specific */ 29 #define CONFIG_HOSTNAME suvd3 30 #define CONFIG_KM_BOARD_NAME "suvd3" 31 32 #define CONFIG_SYS_TEXT_BASE 0xF0000000 33 #define CONFIG_KM_DEF_NETDEV \ 34 "netdev=eth0\0" 35 36 #define CONFIG_KM_DEF_ROOTPATH \ 37 "rootpath=/opt/eldk/ppc_8xx\0" 38 39 /* include common defines/options for all 83xx Keymile boards */ 40 #include "km83xx-common.h" 41 42 #define CONFIG_MISC_INIT_R 1 43 44 /* 45 * System IO Config 46 */ 47 #define CONFIG_SYS_SICRL SICRL_IRQ_CKS 48 49 /* 50 * Hardware Reset Configuration Word 51 */ 52 #define CONFIG_SYS_HRCW_LOW (\ 53 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ 54 HRCWL_DDR_TO_SCB_CLK_2X1 | \ 55 HRCWL_CSB_TO_CLKIN_2X1 | \ 56 HRCWL_CORE_TO_CSB_2_5X1 | \ 57 HRCWL_CE_PLL_VCO_DIV_2 | \ 58 HRCWL_CE_TO_PLL_1X3) 59 60 #define CONFIG_SYS_HRCW_HIGH (\ 61 HRCWH_PCI_AGENT | \ 62 HRCWH_PCI_ARBITER_DISABLE | \ 63 HRCWH_CORE_ENABLE | \ 64 HRCWH_FROM_0X00000100 | \ 65 HRCWH_BOOTSEQ_DISABLE | \ 66 HRCWH_SW_WATCHDOG_DISABLE | \ 67 HRCWH_ROM_LOC_LOCAL_16BIT | \ 68 HRCWH_BIG_ENDIAN | \ 69 HRCWH_LALE_NORMAL) 70 71 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f 72 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ 73 SDRAM_CFG_32_BE | \ 74 SDRAM_CFG_SREN) 75 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 76 #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 77 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ 78 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) 79 80 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ 81 CSCONFIG_ODT_WR_CFG | \ 82 CSCONFIG_ROW_BIT_13 | \ 83 CSCONFIG_COL_BIT_10) 84 85 #define CONFIG_SYS_DDR_MODE 0x47860252 86 #define CONFIG_SYS_DDR_MODE2 0x8080c000 87 88 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ 89 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ 90 (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ 91 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ 92 (0 << TIMING_CFG0_WWT_SHIFT) | \ 93 (0 << TIMING_CFG0_RRT_SHIFT) | \ 94 (0 << TIMING_CFG0_WRT_SHIFT) | \ 95 (0 << TIMING_CFG0_RWT_SHIFT)) 96 97 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ 98 (2 << TIMING_CFG1_WRTORD_SHIFT) | \ 99 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ 100 (2 << TIMING_CFG1_WRREC_SHIFT) | \ 101 (6 << TIMING_CFG1_REFREC_SHIFT) | \ 102 (2 << TIMING_CFG1_ACTTORW_SHIFT) | \ 103 (6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ 104 (2 << TIMING_CFG1_PRETOACT_SHIFT)) 105 106 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ 107 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ 108 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ 109 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ 110 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ 111 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ 112 (5 << TIMING_CFG2_CPO_SHIFT)) 113 114 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 115 116 #define CONFIG_SYS_PIGGY_BASE 0xE8000000 117 #define CONFIG_SYS_PIGGY_SIZE 128 118 #define CONFIG_SYS_APP1_BASE 0xA0000000 119 #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ 120 #define CONFIG_SYS_APP2_BASE 0xB0000000 121 #define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ 122 123 /* EEprom support */ 124 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 125 126 /* 127 * Local Bus Configuration & Clock Setup 128 */ 129 #define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2) 130 #define CONFIG_SYS_LBC_LBCR 0x00000000 131 132 /* 133 * Init Local Bus Memory Controller: 134 * 135 * Bank Bus Machine PortSz Size Device 136 * ---- --- ------- ------ ----- ------ 137 * 2 Local UPMA 16 bit 256MB APP1 138 * 3 Local GPCM 16 bit 256MB APP2 139 * 140 */ 141 142 /* 143 * APP1 on the local bus CS2 144 */ 145 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE 146 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) 147 148 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ 149 BR_PS_16 | \ 150 BR_MS_UPMA | \ 151 BR_V) 152 #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE)) 153 154 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ 155 BR_PS_16 | \ 156 BR_V) 157 158 #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ 159 OR_GPCM_CSNT | \ 160 OR_GPCM_ACS_DIV4 | \ 161 OR_GPCM_SCY_3 | \ 162 OR_GPCM_TRLX) 163 164 #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 165 0x0000c000 | \ 166 MxMR_WLFx_2X) 167 168 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE 169 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) 170 171 /* 172 * MMU Setup 173 */ 174 175 176 /* APP1: icache cacheable, but dcache-inhibit and guarded */ 177 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_10 | \ 178 BATL_MEMCOHERENCE) 179 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | BATU_BL_256M | \ 180 BATU_VS | BATU_VP) 181 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_10 | \ 182 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 183 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 184 185 #ifdef CONFIG_PCI 186 /* PCI MEM space: cacheable */ 187 #define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) 188 #define CFG_IBAT6U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) 189 #define CFG_DBAT6L CFG_IBAT6L 190 #define CFG_DBAT6U CFG_IBAT6U 191 /* PCI MMIO space: cache-inhibit and guarded */ 192 #define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \ 193 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 194 #define CFG_IBAT7U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) 195 #define CFG_DBAT7L CFG_IBAT7L 196 #define CFG_DBAT7U CFG_IBAT7U 197 #else /* CONFIG_PCI */ 198 199 /* APP2: icache cacheable, but dcache-inhibit and guarded */ 200 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_10 | \ 201 BATL_MEMCOHERENCE) 202 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \ 203 BATU_VS | BATU_VP) 204 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_10 | \ 205 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 206 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 207 208 #define CONFIG_SYS_IBAT7L (0) 209 #define CONFIG_SYS_IBAT7U (0) 210 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 211 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 212 #endif /* CONFIG_PCI */ 213 214 #endif /* __CONFIG_H */ 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