xref: /openbmc/u-boot/include/configs/suvd3.h (revision 0fa1fc43)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2006 Freescale Semiconductor, Inc.
4  *                    Dave Liu <daveliu@freescale.com>
5  *
6  * Copyright (C) 2007 Logic Product Development, Inc.
7  *                    Peter Barada <peterb@logicpd.com>
8  *
9  * Copyright (C) 2007 MontaVista Software, Inc.
10  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
11  *
12  * (C) Copyright 2010
13  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
14  */
15 
16 #ifndef __CONFIG_H
17 #define __CONFIG_H
18 
19 /*
20  * High Level Configuration Options
21  */
22 
23 /* This needs to be set prior to including km/km83xx-common.h */
24 
25 #if defined(CONFIG_SUVD3)	/* SUVD3 board specific */
26 #define CONFIG_HOSTNAME		"suvd3"
27 #define CONFIG_KM_BOARD_NAME   "suvd3"
28 /* include common defines/options for all 8321 Keymile boards */
29 #include "km/km8321-common.h"
30 
31 #elif defined(CONFIG_KMVECT1)   /* VECT1 board specific */
32 #define CONFIG_HOSTNAME		"kmvect1"
33 #define CONFIG_KM_BOARD_NAME   "kmvect1"
34 /* at end of uboot partition, before env */
35 #define CONFIG_SYS_QE_FW_ADDR   0xF00B0000
36 /* include common defines/options for all 8309 Keymile boards */
37 #include "km/km8309-common.h"
38 
39 #elif defined(CONFIG_KMTEGR1)   /* TEGR1 board specific */
40 #define CONFIG_HOSTNAME   "kmtegr1"
41 #define CONFIG_KM_BOARD_NAME   "kmtegr1"
42 #define CONFIG_KM_UBI_PARTITION_NAME_BOOT	"ubi0"
43 #define CONFIG_KM_UBI_PARTITION_NAME_APP	"ubi1"
44 
45 #define CONFIG_ENV_ADDR		0xF0100000
46 #define CONFIG_ENV_OFFSET	0x100000
47 
48 #define CONFIG_NAND_ECC_BCH
49 #define CONFIG_NAND_KMETER1
50 #define CONFIG_SYS_MAX_NAND_DEVICE		1
51 #define NAND_MAX_CHIPS				1
52 
53 /* include common defines/options for all 8309 Keymile boards */
54 #include "km/km8309-common.h"
55 /* must be after the include because KMBEC_FPGA is otherwise undefined */
56 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
57 
58 #else
59 #error Supported boards are: SUVD3, KMVECT1, KMTEGR1
60 #endif
61 
62 #define CONFIG_SYS_APP1_BASE		0xA0000000
63 #define CONFIG_SYS_APP1_SIZE		256 /* Megabytes */
64 #define CONFIG_SYS_APP2_BASE		0xB0000000
65 #define CONFIG_SYS_APP2_SIZE		256 /* Megabytes */
66 
67 /* EEprom support */
68 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
69 
70 /*
71  * Init Local Bus Memory Controller:
72  *
73  * Bank Bus     Machine PortSz  Size  Device
74  * ---- ---     ------- ------  -----  ------
75  *  2   Local   UPMA    16 bit  256MB APP1
76  *  3   Local   GPCM    16 bit  256MB APP2
77  *
78  */
79 
80 #if defined(CONFIG_SUVD3) || defined(CONFIG_KMVECT1)
81 /*
82  * APP1 on the local bus CS2
83  */
84 #define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_APP1_BASE
85 #define CONFIG_SYS_LBLAWAR2_PRELIM	(LBLAWAR_EN | LBLAWAR_256MB)
86 
87 #define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_APP1_BASE | \
88 				 BR_PS_16 | \
89 				 BR_MS_UPMA | \
90 				 BR_V)
91 #define CONFIG_SYS_OR2_PRELIM	(MEG_TO_AM(CONFIG_SYS_APP1_SIZE))
92 
93 #define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_APP2_BASE | \
94 				 BR_PS_16 | \
95 				 BR_V)
96 
97 #define CONFIG_SYS_OR3_PRELIM	(MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
98 				 OR_GPCM_CSNT | \
99 				 OR_GPCM_ACS_DIV4 | \
100 				 OR_GPCM_SCY_3 | \
101 				 OR_GPCM_TRLX_SET)
102 
103 #define CONFIG_SYS_MAMR	(MxMR_GPL_x4DIS | \
104 			 0x0000c000 | \
105 			 MxMR_WLFx_2X)
106 
107 #elif defined(CONFIG_KMTEGR1)
108 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \
109 				 BR_PS_16 | \
110 				 BR_MS_GPCM | \
111 				 BR_V)
112 
113 #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
114 				 OR_GPCM_SCY_5 | \
115 				 OR_GPCM_TRLX_CLEAR | \
116 				 OR_GPCM_EHTR_CLEAR)
117 
118 #endif /* CONFIG_KMTEGR1 */
119 
120 #define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_APP2_BASE
121 #define CONFIG_SYS_LBLAWAR3_PRELIM	(LBLAWAR_EN | LBLAWAR_256MB)
122 
123 /*
124  * MMU Setup
125  */
126 #if defined(CONFIG_SUVD3) || defined(CONFIG_KMVECT1)
127 /* APP1:  icache cacheable, but dcache-inhibit and guarded */
128 #define CONFIG_SYS_IBAT5L	(CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
129 				 BATL_MEMCOHERENCE)
130 #define CONFIG_SYS_IBAT5U	(CONFIG_SYS_APP1_BASE | BATU_BL_256M | \
131 				 BATU_VS | BATU_VP)
132 #define CONFIG_SYS_DBAT5L	(CONFIG_SYS_APP1_BASE | BATL_PP_RW | \
133 				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
134 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
135 
136 #elif defined(CONFIG_KMTEGR1)
137 #define CONFIG_SYS_IBAT5L (0)
138 #define CONFIG_SYS_IBAT5U (0)
139 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
140 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
141 #endif /* CONFIG_KMTEGR1 */
142 
143 #define CONFIG_SYS_IBAT6L	(CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
144 				 BATL_MEMCOHERENCE)
145 #define CONFIG_SYS_IBAT6U	(CONFIG_SYS_APP2_BASE | BATU_BL_256M | \
146 				 BATU_VS | BATU_VP)
147 #define CONFIG_SYS_DBAT6L	(CONFIG_SYS_APP2_BASE | BATL_PP_RW | \
148 				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
149 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
150 
151 /*
152  * QE UEC ethernet configuration
153  */
154 #if defined(CONFIG_KMVECT1)
155 #define CONFIG_MV88E6352_SWITCH
156 #define CONFIG_KM_MVEXTSW_ADDR		0x10
157 
158 /* ethernet port connected to simple switch 88e6122 (UEC0) */
159 #define CONFIG_UEC_ETH1
160 #define CONFIG_SYS_UEC1_UCC_NUM		0	/* UCC1 */
161 #define CONFIG_SYS_UEC1_RX_CLK		QE_CLK9
162 #define CONFIG_SYS_UEC1_TX_CLK		QE_CLK10
163 
164 #define CONFIG_FIXED_PHY		0xFFFFFFFF
165 #define CONFIG_SYS_FIXED_PHY_ADDR	0x1E	/* unused address */
166 #define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
167 		{devnum, speed, duplex}
168 #define CONFIG_SYS_FIXED_PHY_PORTS \
169 		CONFIG_SYS_FIXED_PHY_PORT("UEC0", SPEED_100, DUPLEX_FULL)
170 
171 #define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
172 #define CONFIG_SYS_UEC1_PHY_ADDR	CONFIG_SYS_FIXED_PHY_ADDR
173 #define CONFIG_SYS_UEC1_INTERFACE_TYPE	PHY_INTERFACE_MODE_MII
174 #define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
175 #endif /* CONFIG_KMVECT1 */
176 
177 #if defined(CONFIG_KMVECT1) || defined(CONFIG_KMTEGR1)
178 /* ethernet port connected to piggy (UEC2) */
179 #define CONFIG_HAS_ETH1
180 #define CONFIG_UEC_ETH2
181 #define CONFIG_SYS_UEC2_UCC_NUM		2       /* UCC3 */
182 #define CONFIG_SYS_UEC2_RX_CLK		QE_CLK_NONE /* not used in RMII Mode */
183 #define CONFIG_SYS_UEC2_TX_CLK		QE_CLK12
184 #define CONFIG_SYS_UEC2_ETH_TYPE	FAST_ETH
185 #define CONFIG_SYS_UEC2_PHY_ADDR	0
186 #define CONFIG_SYS_UEC2_INTERFACE_TYPE	PHY_INTERFACE_MODE_RMII
187 #define CONFIG_SYS_UEC2_INTERFACE_SPEED	100
188 #endif /* CONFIG_KMVECT1 || CONFIG_KMTEGR1 */
189 
190 #endif /* __CONFIG_H */
191