1 /*
2  * (C) Copyright 2012-2012 Henrik Nordstrom <henrik@henriknordstrom.net>
3  *
4  * (C) Copyright 2007-2011
5  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
6  * Tom Cubie <tangliang@allwinnertech.com>
7  *
8  * Configuration settings for the Allwinner sunxi series of boards.
9  *
10  * SPDX-License-Identifier:	GPL-2.0+
11  */
12 
13 #ifndef _SUNXI_COMMON_CONFIG_H
14 #define _SUNXI_COMMON_CONFIG_H
15 
16 #include <linux/stringify.h>
17 
18 #ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT
19 /*
20  * The U-Boot workarounds bugs in the outdated buggy sunxi-3.4 kernels at the
21  * expense of restricting some features, so the regular machine id values can
22  * be used.
23  */
24 # define CONFIG_MACH_TYPE_COMPAT_REV	0
25 #else
26 /*
27  * A compatibility guard to prevent loading outdated buggy sunxi-3.4 kernels.
28  * Only sunxi-3.4 kernels with appropriate fixes applied are able to pass
29  * beyond the machine id check.
30  */
31 # define CONFIG_MACH_TYPE_COMPAT_REV	1
32 #endif
33 
34 /*
35  * High Level Configuration Options
36  */
37 #define CONFIG_SUNXI		/* sunxi family */
38 #ifdef CONFIG_SPL_BUILD
39 #define CONFIG_SYS_THUMB_BUILD	/* Thumbs mode to save space in SPL */
40 #endif
41 
42 #include <asm/arch/cpu.h>	/* get chip and board defs */
43 
44 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM_SERIAL)
45 # define CONFIG_DW_SERIAL
46 #endif
47 
48 /*
49  * Display CPU information
50  */
51 #define CONFIG_DISPLAY_CPUINFO
52 
53 #define CONFIG_SYS_PROMPT	"sunxi# "
54 
55 /* Serial & console */
56 #define CONFIG_SYS_NS16550
57 #define CONFIG_SYS_NS16550_SERIAL
58 /* ns16550 reg in the low bits of cpu reg */
59 #define CONFIG_SYS_NS16550_CLK		24000000
60 #ifndef CONFIG_DM_SERIAL
61 # define CONFIG_SYS_NS16550_REG_SIZE	-4
62 # define CONFIG_SYS_NS16550_COM1		SUNXI_UART0_BASE
63 # define CONFIG_SYS_NS16550_COM2		SUNXI_UART1_BASE
64 # define CONFIG_SYS_NS16550_COM3		SUNXI_UART2_BASE
65 # define CONFIG_SYS_NS16550_COM4		SUNXI_UART3_BASE
66 # define CONFIG_SYS_NS16550_COM5		SUNXI_R_UART_BASE
67 #endif
68 
69 /* CPU */
70 #define CONFIG_SYS_CACHELINE_SIZE	64
71 
72 /*
73  * The DRAM Base differs between some models. We cannot use macros for the
74  * CONFIG_FOO defines which contain the DRAM base address since they end
75  * up unexpanded in include/autoconf.mk .
76  *
77  * So we have to have this #ifdef #else #endif block for these.
78  */
79 #ifdef CONFIG_MACH_SUN9I
80 #define SDRAM_OFFSET(x) 0x2##x
81 #define CONFIG_SYS_SDRAM_BASE		0x20000000
82 #define CONFIG_SYS_LOAD_ADDR		0x22000000 /* default load address */
83 #define CONFIG_SYS_TEXT_BASE		0x2a000000
84 #define CONFIG_PRE_CON_BUF_ADDR		0x2f000000
85 #define CONFIG_SYS_SPL_MALLOC_START	0x2ff00000
86 #define CONFIG_SPL_BSS_START_ADDR	0x2ff80000
87 #else
88 #define SDRAM_OFFSET(x) 0x4##x
89 #define CONFIG_SYS_SDRAM_BASE		0x40000000
90 #define CONFIG_SYS_LOAD_ADDR		0x42000000 /* default load address */
91 #define CONFIG_SYS_TEXT_BASE		0x4a000000
92 #define CONFIG_PRE_CON_BUF_ADDR		0x4f000000
93 #define CONFIG_SYS_SPL_MALLOC_START	0x4ff00000
94 #define CONFIG_SPL_BSS_START_ADDR	0x4ff80000
95 #endif
96 
97 #define CONFIG_SPL_BSS_MAX_SIZE		0x00080000 /* 512 KiB */
98 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x00080000 /* 512 KiB */
99 
100 #ifdef CONFIG_MACH_SUN9I
101 /*
102  * The A80's A1 sram starts at 0x00010000 rather then at 0x00000000 and is
103  * slightly bigger. Note that it is possible to map the first 32 KiB of the
104  * A1 at 0x00000000 like with older SoCs by writing 0x16aa0001 to the
105  * undocumented 0x008000e0 SYS_CTRL register. Where the 16aa is a key and
106  * the 1 actually activates the mapping of the first 32 KiB to 0x00000000.
107  */
108 #define CONFIG_SYS_INIT_RAM_ADDR	0x10000
109 #define CONFIG_SYS_INIT_RAM_SIZE	0x0a000	/* 40 KiB */
110 #else
111 #define CONFIG_SYS_INIT_RAM_ADDR	0x0
112 #define CONFIG_SYS_INIT_RAM_SIZE	0x8000	/* 32 KiB */
113 #endif
114 
115 #define CONFIG_SYS_INIT_SP_OFFSET \
116 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
117 #define CONFIG_SYS_INIT_SP_ADDR \
118 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
119 
120 #define CONFIG_NR_DRAM_BANKS		1
121 #define PHYS_SDRAM_0			CONFIG_SYS_SDRAM_BASE
122 #define PHYS_SDRAM_0_SIZE		0x80000000 /* 2 GiB */
123 
124 #ifdef CONFIG_AHCI
125 #define CONFIG_LIBATA
126 #define CONFIG_SCSI_AHCI
127 #define CONFIG_SCSI_AHCI_PLAT
128 #define CONFIG_SUNXI_AHCI
129 #define CONFIG_SYS_SCSI_MAX_SCSI_ID	1
130 #define CONFIG_SYS_SCSI_MAX_LUN		1
131 #define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
132 					 CONFIG_SYS_SCSI_MAX_LUN)
133 #define CONFIG_CMD_SCSI
134 #endif
135 
136 #define CONFIG_CMD_MEMORY
137 
138 #define CONFIG_SETUP_MEMORY_TAGS
139 #define CONFIG_CMDLINE_TAG
140 #define CONFIG_INITRD_TAG
141 #define CONFIG_SERIAL_TAG
142 
143 /* mmc config */
144 #if !defined(CONFIG_UART0_PORT_F)
145 #define CONFIG_MMC
146 #define CONFIG_GENERIC_MMC
147 #define CONFIG_CMD_MMC
148 #define CONFIG_MMC_SUNXI
149 #define CONFIG_MMC_SUNXI_SLOT		0
150 #if !defined(CONFIG_SPL_NAND_SUPPORT)
151 #define CONFIG_ENV_IS_IN_MMC
152 #define CONFIG_SYS_MMC_ENV_DEV		0	/* first detected MMC controller */
153 #endif /* CONFIG_SPL_NAND_SUPPORT */
154 #endif
155 
156 /* 4MB of malloc() pool */
157 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (4 << 20))
158 
159 /*
160  * Miscellaneous configurable options
161  */
162 #define CONFIG_CMD_ECHO
163 #define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
164 #define CONFIG_SYS_PBSIZE	1024	/* Print Buffer Size */
165 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
166 #define CONFIG_SYS_GENERIC_BOARD
167 
168 /* Boot Argument Buffer Size */
169 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
170 
171 /* standalone support */
172 #define CONFIG_STANDALONE_LOAD_ADDR	CONFIG_SYS_LOAD_ADDR
173 
174 /* baudrate */
175 #define CONFIG_BAUDRATE			115200
176 
177 /* The stack sizes are set up in start.S using the settings below */
178 #define CONFIG_STACKSIZE		(256 << 10)	/* 256 KiB */
179 
180 /* FLASH and environment organization */
181 
182 #define CONFIG_SYS_NO_FLASH
183 
184 #define CONFIG_SYS_MONITOR_LEN		(512 << 10)	/* 512 KiB */
185 #define CONFIG_IDENT_STRING		" Allwinner Technology"
186 
187 #define CONFIG_ENV_OFFSET		(544 << 10) /* (8 + 24 + 512) KiB */
188 #define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
189 
190 #include <config_cmd_default.h>
191 #undef CONFIG_CMD_FPGA
192 
193 #define CONFIG_FAT_WRITE	/* enable write access */
194 
195 #define CONFIG_SPL_FRAMEWORK
196 #define CONFIG_SPL_LIBCOMMON_SUPPORT
197 #define CONFIG_SPL_SERIAL_SUPPORT
198 #define CONFIG_SPL_LIBGENERIC_SUPPORT
199 
200 #define CONFIG_SPL_BOARD_LOAD_IMAGE
201 
202 #define CONFIG_SPL_TEXT_BASE		0x20		/* sram start+header */
203 #define CONFIG_SPL_MAX_SIZE		0x5fe0		/* 24KB on sun4i/sun7i */
204 
205 #define CONFIG_SPL_LIBDISK_SUPPORT
206 
207 #if !defined(CONFIG_UART0_PORT_F)
208 #define CONFIG_SPL_MMC_SUPPORT
209 #endif
210 
211 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
212 
213 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	80	/* 40KiB */
214 #define CONFIG_SPL_PAD_TO		32768		/* decimal for 'dd' */
215 
216 /* end of 32 KiB in sram */
217 #define LOW_LEVEL_SRAM_STACK		0x00008000 /* End of sram */
218 #define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
219 
220 /* I2C */
221 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER
222 #define CONFIG_SPL_I2C_SUPPORT
223 #endif
224 
225 #if defined CONFIG_I2C0_ENABLE || defined CONFIG_I2C1_ENABLE || \
226     defined CONFIG_I2C2_ENABLE || defined CONFIG_I2C3_ENABLE || \
227     defined CONFIG_I2C4_ENABLE
228 #define CONFIG_SYS_I2C
229 #define CONFIG_SYS_I2C_MVTWSI
230 #define CONFIG_SYS_I2C_SPEED		400000
231 #define CONFIG_SYS_I2C_SLAVE		0x7f
232 #define CONFIG_CMD_I2C
233 #endif
234 
235 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
236 #define CONFIG_SYS_I2C_SOFT
237 #define CONFIG_SYS_I2C_SOFT_SPEED	50000
238 #define CONFIG_SYS_I2C_SOFT_SLAVE	0x00
239 /* We use pin names in Kconfig and sunxi_name_to_gpio() */
240 #define CONFIG_SOFT_I2C_GPIO_SDA	soft_i2c_gpio_sda
241 #define CONFIG_SOFT_I2C_GPIO_SCL	soft_i2c_gpio_scl
242 #ifndef __ASSEMBLY__
243 extern int soft_i2c_gpio_sda;
244 extern int soft_i2c_gpio_scl;
245 #endif
246 #define CONFIG_VIDEO_LCD_I2C_BUS	0 /* The lcd panel soft i2c is bus 0 */
247 #define CONFIG_SYS_SPD_BUS_NUM		1 /* And the axp209 i2c bus is bus 1 */
248 #else
249 #define CONFIG_SYS_SPD_BUS_NUM		0 /* The axp209 i2c bus is bus 0 */
250 #define CONFIG_VIDEO_LCD_I2C_BUS	-1 /* NA, but necessary to compile */
251 #endif
252 
253 /* PMU */
254 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || defined CONFIG_AXP221_POWER
255 #define CONFIG_SPL_POWER_SUPPORT
256 #endif
257 
258 #ifndef CONFIG_CONS_INDEX
259 #define CONFIG_CONS_INDEX              1       /* UART0 */
260 #endif
261 
262 #if CONFIG_CONS_INDEX == 1
263 #ifdef CONFIG_MACH_SUN9I
264 #define OF_STDOUT_PATH		"/soc/serial@07000000:115200"
265 #else
266 #define OF_STDOUT_PATH		"/soc@01c00000/serial@01c28000:115200"
267 #endif
268 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
269 #define OF_STDOUT_PATH		"/soc@01c00000/serial@01c28400:115200"
270 #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
271 #define OF_STDOUT_PATH		"/soc@01c00000/serial@01c28800:115200"
272 #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
273 #define OF_STDOUT_PATH		"/soc@01c00000/serial@01f02800:115200"
274 #else
275 #error Unsupported console port nr. Please fix stdout-path in sunxi-common.h.
276 #endif
277 
278 /* GPIO */
279 #define CONFIG_SUNXI_GPIO
280 #define CONFIG_SPL_GPIO_SUPPORT
281 #define CONFIG_CMD_GPIO
282 
283 #ifdef CONFIG_VIDEO
284 /*
285  * The amount of RAM to keep free at the top of RAM when relocating u-boot,
286  * to use as framebuffer. This must be a multiple of 4096.
287  */
288 #define CONFIG_SUNXI_MAX_FB_SIZE (9 << 20)
289 
290 /* Do we want to initialize a simple FB? */
291 #define CONFIG_VIDEO_DT_SIMPLEFB
292 
293 #define CONFIG_VIDEO_SUNXI
294 
295 #define CONFIG_CFB_CONSOLE
296 #define CONFIG_VIDEO_SW_CURSOR
297 #define CONFIG_VIDEO_LOGO
298 #define CONFIG_VIDEO_STD_TIMINGS
299 #define CONFIG_I2C_EDID
300 
301 /* allow both serial and cfb console. */
302 #define CONFIG_CONSOLE_MUX
303 /* stop x86 thinking in cfbconsole from trying to init a pc keyboard */
304 #define CONFIG_VGA_AS_SINGLE_DEVICE
305 
306 /* To be able to hook simplefb into dt */
307 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
308 #define CONFIG_OF_BOARD_SETUP
309 #endif
310 
311 #endif /* CONFIG_VIDEO */
312 
313 /* Ethernet support */
314 #ifdef CONFIG_SUNXI_EMAC
315 #define CONFIG_PHY_ADDR		1
316 #define CONFIG_MII			/* MII PHY management		*/
317 #define CONFIG_PHYLIB
318 #endif
319 
320 #ifdef CONFIG_SUNXI_GMAC
321 #define CONFIG_DW_AUTONEG
322 #define CONFIG_PHY_GIGE			/* GMAC can use gigabit PHY	*/
323 #define CONFIG_PHY_ADDR		1
324 #define CONFIG_MII			/* MII PHY management		*/
325 #define CONFIG_PHYLIB
326 #endif
327 
328 #ifdef CONFIG_USB_EHCI
329 #define CONFIG_USB_OHCI_NEW
330 #define CONFIG_USB_OHCI_SUNXI
331 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
332 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
333 #endif
334 
335 #ifdef CONFIG_USB_MUSB_SUNXI
336 #define CONFIG_MUSB_HOST
337 #define CONFIG_MUSB_PIO_ONLY
338 #endif
339 
340 #if defined CONFIG_USB_EHCI || defined CONFIG_USB_MUSB_SUNXI
341 #define CONFIG_CMD_USB
342 #define CONFIG_USB_STORAGE
343 #endif
344 
345 #ifdef CONFIG_USB_KEYBOARD
346 #define CONFIG_CONSOLE_MUX
347 #define CONFIG_PREBOOT
348 #define CONFIG_SYS_STDIO_DEREGISTER
349 #define CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
350 #endif
351 
352 #if !defined CONFIG_ENV_IS_IN_MMC && \
353     !defined CONFIG_ENV_IS_IN_NAND && \
354     !defined CONFIG_ENV_IS_IN_FAT && \
355     !defined CONFIG_ENV_IS_IN_SPI_FLASH
356 #define CONFIG_ENV_IS_NOWHERE
357 #endif
358 
359 #ifdef CONFIG_SPL_NAND_SUPPORT
360 #define CONFIG_NAND
361 #define CONFIG_SYS_NAND_SELF_INIT
362 #define CONFIG_NAND_SUNXI
363 #define CONFIG_CMD_SPL_WRITE_SIZE		0x000400
364 #define CONFIG_SYS_NAND_U_BOOT_OFFS		0x008000
365 
366 /* \todo Make these parameterisable in kernel config ? */
367 #define CONFIG_NAND_SUNXI_PAGE_SIZE		8192
368 #define CONFIG_NAND_SUNXI_ECC_STEP		1024
369 #define CONFIG_NAND_SUNXI_ECC_STRENGTH		40
370 #define CONFIG_NAND_SUNXI_ADDR_CYCLES		5
371 
372 #ifndef CONFIG_NAND_SUNXI_GPC_PORTS
373 #error "No NAND GPC ports defined, NAND unsupported"
374 #endif
375 #endif /* CONFIG_SPL_NAND_SUPPORT */
376 
377 #define CONFIG_MISC_INIT_R
378 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
379 
380 #ifndef CONFIG_SPL_BUILD
381 #include <config_distro_defaults.h>
382 
383 /* Enable pre-console buffer to get complete log on the VGA console */
384 #define CONFIG_PRE_CONSOLE_BUFFER
385 #define CONFIG_PRE_CON_BUF_SZ		4096 /* Aprox 2 80*25 screens */
386 
387 /*
388  * 240M RAM (256M minimum minus space for the framebuffer),
389  * 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
390  * 1M script, 1M pxe and the ramdisk at the end.
391  */
392 #define MEM_LAYOUT_ENV_SETTINGS \
393 	"bootm_size=0xf000000\0" \
394 	"kernel_addr_r=" __stringify(SDRAM_OFFSET(2000000)) "\0" \
395 	"fdt_addr_r=" __stringify(SDRAM_OFFSET(3000000)) "\0" \
396 	"scriptaddr=" __stringify(SDRAM_OFFSET(3100000)) "\0" \
397 	"pxefile_addr_r=" __stringify(SDRAM_OFFSET(3200000)) "\0" \
398 	"ramdisk_addr_r=" __stringify(SDRAM_OFFSET(3300000)) "\0"
399 
400 #ifdef CONFIG_MMC
401 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
402 #else
403 #define BOOT_TARGET_DEVICES_MMC(func)
404 #endif
405 
406 #ifdef CONFIG_AHCI
407 #define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0)
408 #else
409 #define BOOT_TARGET_DEVICES_SCSI(func)
410 #endif
411 
412 #ifdef CONFIG_USB_EHCI
413 #define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
414 #else
415 #define BOOT_TARGET_DEVICES_USB(func)
416 #endif
417 
418 #define BOOT_TARGET_DEVICES(func) \
419 	BOOT_TARGET_DEVICES_MMC(func) \
420 	BOOT_TARGET_DEVICES_SCSI(func) \
421 	BOOT_TARGET_DEVICES_USB(func) \
422 	func(PXE, pxe, na) \
423 	func(DHCP, dhcp, na)
424 
425 #include <config_distro_bootcmd.h>
426 
427 #ifdef CONFIG_USB_KEYBOARD
428 #define CONSOLE_STDIN_SETTINGS \
429 	"preboot=usb start\0" \
430 	"stdin=serial,usbkbd\0"
431 #else
432 #define CONSOLE_STDIN_SETTINGS \
433 	"stdin=serial\0"
434 #endif
435 
436 #ifdef CONFIG_VIDEO
437 #define CONSOLE_STDOUT_SETTINGS \
438 	"stdout=serial,vga\0" \
439 	"stderr=serial,vga\0"
440 #else
441 #define CONSOLE_STDOUT_SETTINGS \
442 	"stdout=serial\0" \
443 	"stderr=serial\0"
444 #endif
445 
446 #define CONSOLE_ENV_SETTINGS \
447 	CONSOLE_STDIN_SETTINGS \
448 	CONSOLE_STDOUT_SETTINGS
449 
450 #define CONFIG_EXTRA_ENV_SETTINGS \
451 	CONSOLE_ENV_SETTINGS \
452 	MEM_LAYOUT_ENV_SETTINGS \
453 	"fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
454 	"console=ttyS0,115200\0" \
455 	BOOTENV
456 
457 #else /* ifndef CONFIG_SPL_BUILD */
458 #define CONFIG_EXTRA_ENV_SETTINGS
459 #endif
460 
461 #endif /* _SUNXI_COMMON_CONFIG_H */
462