1 /* 2 * (C) Copyright 2014 3 * Vikas Manocha, STMicroelectronics, <vikas.manocha@st.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __CONFIG_STV0991_H 9 #define __CONFIG_STV0991_H 10 #define CONFIG_SYS_DCACHE_OFF 11 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH 12 13 #define CONFIG_SYS_CORTEX_R4 14 15 #define CONFIG_SYS_NO_FLASH 16 17 /* ram memory-related information */ 18 #define CONFIG_NR_DRAM_BANKS 1 19 #define PHYS_SDRAM_1 0x00000000 20 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 21 #define PHYS_SDRAM_1_SIZE 0x00198000 22 23 #define CONFIG_ENV_SIZE 0x10000 24 #define CONFIG_ENV_IS_IN_SPI_FLASH 25 #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE 26 #define CONFIG_ENV_OFFSET 0x30000 27 #define CONFIG_ENV_ADDR \ 28 (PHYS_SDRAM_1_SIZE - CONFIG_ENV_SIZE) 29 #define CONFIG_SYS_MAXARGS 16 30 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024) 31 32 /* serial port (PL011) configuration */ 33 #define CONFIG_BAUDRATE 115200 34 #define CONFIG_PL01X_SERIAL 35 36 /* user interface */ 37 #define CONFIG_SYS_CBSIZE 1024 38 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ 39 +sizeof(CONFIG_SYS_PROMPT) + 16) 40 41 /* MISC */ 42 #define CONFIG_SYS_LOAD_ADDR 0x00000000 43 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 44 #define CONFIG_SYS_INIT_RAM_ADDR 0x00190000 45 #define CONFIG_SYS_INIT_SP_OFFSET \ 46 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 47 /* U-Boot Load Address */ 48 #define CONFIG_SYS_TEXT_BASE 0x00010000 49 #define CONFIG_SYS_INIT_SP_ADDR \ 50 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 51 52 /* GMAC related configs */ 53 54 #define CONFIG_MII 55 #define CONFIG_DW_ALTDESCRIPTOR 56 #define CONFIG_PHY_MICREL 57 58 /* Command support defines */ 59 #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ 60 61 #define CONFIG_SYS_MEMTEST_START 0x0000 62 #define CONFIG_SYS_MEMTEST_END 1024*1024 63 64 /* Misc configuration */ 65 #define CONFIG_SYS_LONGHELP 66 #define CONFIG_CMDLINE_EDITING 67 68 #define CONFIG_BOOTCOMMAND "go 0x40040000" 69 70 /* 71 + * QSPI support 72 + */ 73 #ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */ 74 #define CONFIG_CQSPI_DECODER 0 75 #define CONFIG_CQSPI_REF_CLK ((30/4)/2)*1000*1000 76 #define CONFIG_BOUNCE_BUFFER 77 78 #endif 79 80 #endif /* __CONFIG_H */ 81