xref: /openbmc/u-boot/include/configs/stv0991.h (revision a22bbfda)
1 /*
2  * (C) Copyright 2014
3  * Vikas Manocha, STMicroelectronics, <vikas.manocha@st.com>
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #ifndef __CONFIG_STV0991_H
9 #define __CONFIG_STV0991_H
10 #define CONFIG_SYS_DCACHE_OFF
11 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
12 
13 #define CONFIG_SYS_CORTEX_R4
14 
15 /* ram memory-related information */
16 #define CONFIG_NR_DRAM_BANKS			1
17 #define PHYS_SDRAM_1				0x00000000
18 #define CONFIG_SYS_SDRAM_BASE			PHYS_SDRAM_1
19 #define PHYS_SDRAM_1_SIZE			0x00198000
20 
21 #define CONFIG_ENV_SIZE				0x10000
22 #define CONFIG_ENV_SECT_SIZE			CONFIG_ENV_SIZE
23 #define CONFIG_ENV_OFFSET			0x30000
24 #define CONFIG_ENV_ADDR				\
25 	(PHYS_SDRAM_1_SIZE - CONFIG_ENV_SIZE)
26 #define CONFIG_SYS_MAXARGS			16
27 #define CONFIG_SYS_MALLOC_LEN			(CONFIG_ENV_SIZE + 16 * 1024)
28 
29 /* serial port (PL011) configuration */
30 #define CONFIG_PL01X_SERIAL
31 
32 /* user interface */
33 #define CONFIG_SYS_CBSIZE			1024
34 #define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE \
35 						+sizeof(CONFIG_SYS_PROMPT) + 16)
36 
37 /* MISC */
38 #define CONFIG_SYS_LOAD_ADDR			0x00000000
39 #define CONFIG_SYS_INIT_RAM_SIZE		0x8000
40 #define CONFIG_SYS_INIT_RAM_ADDR		0x00190000
41 #define CONFIG_SYS_INIT_SP_OFFSET		\
42 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
43 /* U-Boot Load Address */
44 #define CONFIG_SYS_TEXT_BASE			0x00010000
45 #define CONFIG_SYS_INIT_SP_ADDR			\
46 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
47 
48 /* GMAC related configs */
49 
50 #define CONFIG_MII
51 #define CONFIG_DW_ALTDESCRIPTOR
52 
53 /* Command support defines */
54 #define CONFIG_PHY_RESET_DELAY			10000		/* in usec */
55 
56 #define CONFIG_SYS_MEMTEST_START               0x0000
57 #define CONFIG_SYS_MEMTEST_END                 1024*1024
58 
59 /* Misc configuration */
60 #define CONFIG_SYS_LONGHELP
61 #define CONFIG_CMDLINE_EDITING
62 
63 #define CONFIG_BOOTCOMMAND                     "go 0x40040000"
64 
65 /*
66 + * QSPI support
67 + */
68 #ifdef CONFIG_OF_CONTROL		/* QSPI is controlled via DT */
69 #define CONFIG_CQSPI_DECODER		0
70 #define CONFIG_CQSPI_REF_CLK		((30/4)/2)*1000*1000
71 #define CONFIG_BOUNCE_BUFFER
72 
73 #endif
74 
75 #endif /* __CONFIG_H */
76