1 /* 2 * Copyright (C) 2014, STMicroelectronics - All Rights Reserved 3 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __CONFIG_STV0991_H 9 #define __CONFIG_STV0991_H 10 #define CONFIG_SYS_DCACHE_OFF 11 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH 12 13 #define CONFIG_SYS_CORTEX_R4 14 15 /* ram memory-related information */ 16 #define CONFIG_NR_DRAM_BANKS 1 17 #define PHYS_SDRAM_1 0x00000000 18 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 19 #define PHYS_SDRAM_1_SIZE 0x00198000 20 21 #define CONFIG_ENV_SIZE 0x10000 22 #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE 23 #define CONFIG_ENV_OFFSET 0x30000 24 #define CONFIG_ENV_ADDR \ 25 (PHYS_SDRAM_1_SIZE - CONFIG_ENV_SIZE) 26 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024) 27 28 /* serial port (PL011) configuration */ 29 #define CONFIG_PL01X_SERIAL 30 31 /* user interface */ 32 #define CONFIG_SYS_CBSIZE 1024 33 34 /* MISC */ 35 #define CONFIG_SYS_LOAD_ADDR 0x00000000 36 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 37 #define CONFIG_SYS_INIT_RAM_ADDR 0x00190000 38 #define CONFIG_SYS_INIT_SP_OFFSET \ 39 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 40 /* U-Boot Load Address */ 41 #define CONFIG_SYS_TEXT_BASE 0x00010000 42 #define CONFIG_SYS_INIT_SP_ADDR \ 43 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 44 45 /* GMAC related configs */ 46 47 #define CONFIG_MII 48 #define CONFIG_DW_ALTDESCRIPTOR 49 50 /* Command support defines */ 51 #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ 52 53 #define CONFIG_SYS_MEMTEST_START 0x0000 54 #define CONFIG_SYS_MEMTEST_END 1024*1024 55 56 /* Misc configuration */ 57 #define CONFIG_SYS_LONGHELP 58 #define CONFIG_CMDLINE_EDITING 59 60 #define CONFIG_BOOTCOMMAND "go 0x40040000" 61 62 /* 63 + * QSPI support 64 + */ 65 #ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */ 66 #define CONFIG_CQSPI_REF_CLK ((30/4)/2)*1000*1000 67 68 #endif 69 70 #endif /* __CONFIG_H */ 71