1 /* 2 * (C) Copyright 2014 3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de 4 * 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 /* E300 family */ 16 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 17 #define CONFIG_MPC830x 1 /* MPC830x family */ 18 #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ 19 #define CONFIG_STRIDER 1 /* STRIDER board specific */ 20 21 #define CONFIG_SYS_TEXT_BASE 0xFE000000 22 23 #define CONFIG_BOARD_EARLY_INIT_R 24 #define CONFIG_LAST_STAGE_INIT 25 26 #define CONFIG_FSL_ESDHC 27 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 28 29 #define CONFIG_SYS_ALT_MEMTEST 30 31 #define CONFIG_CMD_IOLOOP 32 33 /* 34 * System Clock Setup 35 */ 36 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 37 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 38 39 /* 40 * Hardware Reset Configuration Word 41 * if CLKIN is 66.66MHz, then 42 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz 43 * We choose the A type silicon as default, so the core is 400Mhz. 44 */ 45 #define CONFIG_SYS_HRCW_LOW (\ 46 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 47 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 48 HRCWL_SVCOD_DIV_2 |\ 49 HRCWL_CSB_TO_CLKIN_4X1 |\ 50 HRCWL_CORE_TO_CSB_3X1) 51 /* 52 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits 53 * in 8308's HRCWH according to the manual, but original Freescale's 54 * code has them and I've expirienced some problems using the board 55 * with BDI3000 attached when I've tried to set these bits to zero 56 * (UART doesn't work after the 'reset run' command). 57 */ 58 #define CONFIG_SYS_HRCW_HIGH (\ 59 HRCWH_PCI_HOST |\ 60 HRCWH_PCI1_ARBITER_ENABLE |\ 61 HRCWH_CORE_ENABLE |\ 62 HRCWH_FROM_0XFFF00100 |\ 63 HRCWH_BOOTSEQ_DISABLE |\ 64 HRCWH_SW_WATCHDOG_DISABLE |\ 65 HRCWH_ROM_LOC_LOCAL_16BIT |\ 66 HRCWH_RL_EXT_LEGACY |\ 67 HRCWH_TSEC1M_IN_MII |\ 68 HRCWH_TSEC2M_IN_RGMII |\ 69 HRCWH_BIG_ENDIAN) 70 71 /* 72 * System IO Config 73 */ 74 #define CONFIG_SYS_SICRH (\ 75 SICRH_ESDHC_A_SD |\ 76 SICRH_ESDHC_B_SD |\ 77 SICRH_ESDHC_C_SD |\ 78 SICRH_GPIO_A_GPIO |\ 79 SICRH_GPIO_B_GPIO |\ 80 SICRH_IEEE1588_A_GPIO |\ 81 SICRH_USB |\ 82 SICRH_GTM_GPIO |\ 83 SICRH_IEEE1588_B_GPIO |\ 84 SICRH_ETSEC2_GPIO |\ 85 SICRH_GPIOSEL_1 |\ 86 SICRH_TMROBI_V3P3 |\ 87 SICRH_TSOBI1_V2P5 |\ 88 SICRH_TSOBI2_V2P5) /* 0x0037f103 */ 89 #define CONFIG_SYS_SICRL (\ 90 SICRL_SPI_PF0 |\ 91 SICRL_UART_PF0 |\ 92 SICRL_IRQ_PF0 |\ 93 SICRL_I2C2_PF0 |\ 94 SICRL_ETSEC1_TX_CLK) /* 0x00000000 */ 95 96 /* 97 * IMMR new address 98 */ 99 #define CONFIG_SYS_IMMR 0xE0000000 100 101 /* 102 * SERDES 103 */ 104 #define CONFIG_FSL_SERDES 105 #define CONFIG_FSL_SERDES1 0xe3000 106 107 /* 108 * Arbiter Setup 109 */ 110 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 111 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 112 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 113 114 /* 115 * DDR Setup 116 */ 117 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 118 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 119 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 120 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 121 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 122 | DDRCDR_PZ_LOZ \ 123 | DDRCDR_NZ_LOZ \ 124 | DDRCDR_ODT \ 125 | DDRCDR_Q_DRN) 126 /* 0x7b880001 */ 127 /* 128 * Manually set up DDR parameters 129 * consist of one chip NT5TU64M16HG from NANYA 130 */ 131 132 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 133 134 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 135 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 136 | CSCONFIG_ODT_RD_NEVER \ 137 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 138 | CSCONFIG_BANK_BIT_3 \ 139 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 140 /* 0x80010102 */ 141 #define CONFIG_SYS_DDR_TIMING_3 0 142 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 143 | (0 << TIMING_CFG0_WRT_SHIFT) \ 144 | (0 << TIMING_CFG0_RRT_SHIFT) \ 145 | (0 << TIMING_CFG0_WWT_SHIFT) \ 146 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 147 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 148 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 149 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 150 /* 0x00260802 */ 151 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 152 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 153 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 154 | (7 << TIMING_CFG1_CASLAT_SHIFT) \ 155 | (9 << TIMING_CFG1_REFREC_SHIFT) \ 156 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 157 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 158 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 159 /* 0x26279222 */ 160 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ 161 | (4 << TIMING_CFG2_CPO_SHIFT) \ 162 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 163 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 164 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 165 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 166 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 167 /* 0x021848c5 */ 168 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \ 169 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 170 /* 0x08240100 */ 171 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 172 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 173 | SDRAM_CFG_DBW_16) 174 /* 0x43100000 */ 175 176 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 177 #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ 178 | (0x0242 << SDRAM_MODE_SD_SHIFT)) 179 /* ODT 150ohm CL=4, AL=0 on SDRAM */ 180 #define CONFIG_SYS_DDR_MODE2 0x00000000 181 182 /* 183 * Memory test 184 */ 185 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ 186 #define CONFIG_SYS_MEMTEST_END 0x07f00000 187 188 /* 189 * The reserved memory 190 */ 191 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 192 193 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 194 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 195 196 /* 197 * Initial RAM Base Address Setup 198 */ 199 #define CONFIG_SYS_INIT_RAM_LOCK 1 200 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 201 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 202 #define CONFIG_SYS_GBL_DATA_OFFSET \ 203 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 204 205 /* 206 * Local Bus Configuration & Clock Setup 207 */ 208 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 209 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 210 #define CONFIG_SYS_LBC_LBCR 0x00040000 211 212 /* 213 * FLASH on the Local Bus 214 */ 215 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 216 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 217 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 218 #define CONFIG_FLASH_CFI_LEGACY 219 #define CONFIG_SYS_FLASH_LEGACY_512Kx16 220 221 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 222 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ 223 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 224 225 /* Window base at flash base */ 226 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 227 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 228 229 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 230 | BR_PS_16 /* 16 bit port */ \ 231 | BR_MS_GPCM /* MSEL = GPCM */ \ 232 | BR_V) /* valid */ 233 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 234 | OR_UPM_XAM \ 235 | OR_GPCM_CSNT \ 236 | OR_GPCM_ACS_DIV2 \ 237 | OR_GPCM_XACS \ 238 | OR_GPCM_SCY_15 \ 239 | OR_GPCM_TRLX_SET \ 240 | OR_GPCM_EHTR_SET) 241 242 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 243 #define CONFIG_SYS_MAX_FLASH_SECT 135 244 245 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 246 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 247 248 /* 249 * FPGA 250 */ 251 #define CONFIG_SYS_FPGA0_BASE 0xE0600000 252 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ 253 254 /* Window base at FPGA base */ 255 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE 256 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB) 257 258 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \ 259 | BR_PS_16 /* 16 bit port */ \ 260 | BR_MS_GPCM /* MSEL = GPCM */ \ 261 | BR_V) /* valid */ 262 263 #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \ 264 | OR_UPM_XAM \ 265 | OR_GPCM_CSNT \ 266 | OR_GPCM_SCY_5 \ 267 | OR_GPCM_TRLX_CLEAR \ 268 | OR_GPCM_EHTR_CLEAR) 269 270 #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE 271 #define CONFIG_SYS_FPGA_DONE(k) 0x0010 272 273 #define CONFIG_SYS_FPGA_COUNT 1 274 275 #define CONFIG_SYS_MCLINK_MAX 3 276 277 #define CONFIG_SYS_FPGA_PTR \ 278 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL } 279 280 #define CONFIG_SYS_FPGA_NO_RFL_HI 281 282 /* 283 * Serial Port 284 */ 285 #define CONFIG_CONS_INDEX 2 286 #define CONFIG_SYS_NS16550_SERIAL 287 #define CONFIG_SYS_NS16550_REG_SIZE 1 288 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 289 290 #define CONFIG_SYS_BAUDRATE_TABLE \ 291 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 292 293 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 294 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 295 296 /* Pass open firmware flat tree */ 297 298 /* I2C */ 299 #define CONFIG_SYS_I2C 300 #define CONFIG_SYS_I2C_FSL 301 #define CONFIG_SYS_FSL_I2C_SPEED 400000 302 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 303 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 304 305 #define CONFIG_PCA953X /* NXP PCA9554 */ 306 #define CONFIG_CMD_PCA953X 307 #define CONFIG_CMD_PCA953X_INFO 308 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x24, 16}, {0x25, 16}, {0x26, 16}, \ 309 {0x3c, 8}, {0x3d, 8}, {0x3e, 8} } 310 311 #define CONFIG_PCA9698 /* NXP PCA9698 */ 312 313 #define CONFIG_SYS_I2C_IHS 314 #define CONFIG_SYS_I2C_IHS_CH0 315 #define CONFIG_SYS_I2C_IHS_SPEED_0 50000 316 #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F 317 #define CONFIG_SYS_I2C_IHS_CH1 318 #define CONFIG_SYS_I2C_IHS_SPEED_1 50000 319 #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F 320 #define CONFIG_SYS_I2C_IHS_CH2 321 #define CONFIG_SYS_I2C_IHS_SPEED_2 50000 322 #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F 323 #define CONFIG_SYS_I2C_IHS_CH3 324 #define CONFIG_SYS_I2C_IHS_SPEED_3 50000 325 #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F 326 327 #ifdef CONFIG_STRIDER_CON_DP 328 #define CONFIG_SYS_I2C_IHS_DUAL 329 #define CONFIG_SYS_I2C_IHS_CH0_1 330 #define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000 331 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F 332 #define CONFIG_SYS_I2C_IHS_CH1_1 333 #define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000 334 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F 335 #define CONFIG_SYS_I2C_IHS_CH2_1 336 #define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000 337 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F 338 #define CONFIG_SYS_I2C_IHS_CH3_1 339 #define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000 340 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F 341 #endif 342 343 /* 344 * Software (bit-bang) I2C driver configuration 345 */ 346 #define CONFIG_SYS_I2C_SOFT 347 #define CONFIG_SOFT_I2C_READ_REPEATED_START 348 #define CONFIG_SYS_I2C_SOFT_SPEED 50000 349 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F 350 #define I2C_SOFT_DECLARATIONS2 351 #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 352 #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F 353 #define I2C_SOFT_DECLARATIONS3 354 #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000 355 #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F 356 #define I2C_SOFT_DECLARATIONS4 357 #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 358 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F 359 #if defined(CONFIG_STRIDER_CON) || defined(CONFIG_STRIDER_CON_DP) 360 #define I2C_SOFT_DECLARATIONS5 361 #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000 362 #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F 363 #define I2C_SOFT_DECLARATIONS6 364 #define CONFIG_SYS_I2C_SOFT_SPEED_6 50000 365 #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F 366 #define I2C_SOFT_DECLARATIONS7 367 #define CONFIG_SYS_I2C_SOFT_SPEED_7 50000 368 #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F 369 #define I2C_SOFT_DECLARATIONS8 370 #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000 371 #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F 372 #endif 373 #ifdef CONFIG_STRIDER_CON_DP 374 #define I2C_SOFT_DECLARATIONS9 375 #define CONFIG_SYS_I2C_SOFT_SPEED_9 50000 376 #define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F 377 #define I2C_SOFT_DECLARATIONS10 378 #define CONFIG_SYS_I2C_SOFT_SPEED_10 50000 379 #define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F 380 #define I2C_SOFT_DECLARATIONS11 381 #define CONFIG_SYS_I2C_SOFT_SPEED_11 50000 382 #define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F 383 #define I2C_SOFT_DECLARATIONS12 384 #define CONFIG_SYS_I2C_SOFT_SPEED_12 50000 385 #define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F 386 #endif 387 388 #ifdef CONFIG_STRIDER_CON 389 #define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8} 390 #define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8} 391 #define CONFIG_SYS_ADV7611_I2C {5, 6, 7, 8} 392 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 393 #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \ 394 {12, 0x4c} } 395 #elif defined(CONFIG_STRIDER_CON_DP) 396 #define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20} 397 #define CONFIG_SYS_CH7301_I2C {1, 3, 5, 7} 398 #define CONFIG_SYS_ADV7611_I2C {1, 3, 5, 7} 399 #define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8} 400 #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \ 401 {12, 0x4c} } 402 #elif defined(CONFIG_STRIDER_CPU_DP) 403 #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4} 404 #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4} 405 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 406 #define CONFIG_STRIDER_FANS { {6, 0x4c}, {7, 0x4c}, \ 407 {8, 0x4c} } 408 #else 409 #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4} 410 #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4} 411 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 412 #define CONFIG_STRIDER_FANS { {2, 0x18}, {3, 0x18}, \ 413 {4, 0x18} } 414 #endif 415 416 #ifndef __ASSEMBLY__ 417 void fpga_gpio_set(unsigned int bus, int pin); 418 void fpga_gpio_clear(unsigned int bus, int pin); 419 int fpga_gpio_get(unsigned int bus, int pin); 420 void fpga_control_set(unsigned int bus, int pin); 421 void fpga_control_clear(unsigned int bus, int pin); 422 #endif 423 424 #ifdef CONFIG_STRIDER_CON 425 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040) 426 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020) 427 #define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \ 428 (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR) 429 #elif defined(CONFIG_STRIDER_CON_DP) 430 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200) 431 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100) 432 #define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4) 433 #else 434 #define I2C_SDA_GPIO 0x0040 435 #define I2C_SCL_GPIO 0x0020 436 #define I2C_FPGA_IDX I2C_ADAP_HWNR 437 #endif 438 439 #ifdef CONFIG_STRIDER_CON_DP 440 #define I2C_ACTIVE \ 441 do { \ 442 if (I2C_ADAP_HWNR > 7) \ 443 fpga_control_set(I2C_FPGA_IDX, 0x0004); \ 444 else \ 445 fpga_control_clear(I2C_FPGA_IDX, 0x0004); \ 446 } while (0) 447 #else 448 #define I2C_ACTIVE { } 449 #endif 450 451 #define I2C_TRISTATE { } 452 #define I2C_READ \ 453 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0) 454 #define I2C_SDA(bit) \ 455 do { \ 456 if (bit) \ 457 fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \ 458 else \ 459 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \ 460 } while (0) 461 #define I2C_SCL(bit) \ 462 do { \ 463 if (bit) \ 464 fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \ 465 else \ 466 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \ 467 } while (0) 468 #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ 469 470 /* 471 * Software (bit-bang) MII driver configuration 472 */ 473 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 474 #define CONFIG_BITBANGMII_MULTI 475 476 /* 477 * OSD Setup 478 */ 479 #define CONFIG_SYS_OSD_SCREENS 1 480 #define CONFIG_SYS_DP501_DIFFERENTIAL 481 #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ 482 483 #ifdef CONFIG_STRIDER_CON_DP 484 #define CONFIG_SYS_OSD_DH 485 #endif 486 487 /* 488 * General PCI 489 * Addresses are mapped 1-1. 490 */ 491 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 492 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 493 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 494 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 495 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 496 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 497 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 498 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 499 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 500 501 /* enable PCIE clock */ 502 #define CONFIG_SYS_SCCR_PCIEXP1CM 1 503 504 #define CONFIG_PCI_INDIRECT_BRIDGE 505 #define CONFIG_PCIE 506 507 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 508 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 509 510 /* 511 * TSEC 512 */ 513 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 514 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 515 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 516 517 /* 518 * TSEC ethernet configuration 519 */ 520 #define CONFIG_MII 1 /* MII PHY management */ 521 #define CONFIG_TSEC1 522 #define CONFIG_TSEC1_NAME "eTSEC0" 523 #define TSEC1_PHY_ADDR 1 524 #define TSEC1_PHYIDX 0 525 #define TSEC1_FLAGS 0 526 527 /* Options are: eTSEC[0-1] */ 528 #define CONFIG_ETHPRIME "eTSEC0" 529 530 /* 531 * Environment 532 */ 533 #if 1 534 #define CONFIG_ENV_IS_IN_FLASH 1 535 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 536 CONFIG_SYS_MONITOR_LEN) 537 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 538 #define CONFIG_ENV_SIZE 0x2000 539 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 540 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 541 #else 542 #define CONFIG_ENV_IS_NOWHERE 543 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 544 #endif 545 546 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 547 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 548 549 /* 550 * Command line configuration. 551 */ 552 #define CONFIG_CMD_PCI 553 554 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 555 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 556 557 /* 558 * Miscellaneous configurable options 559 */ 560 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 561 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 562 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 563 564 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 565 566 /* Print Buffer Size */ 567 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 568 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 569 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 570 571 /* 572 * For booting Linux, the board info and command line data 573 * have to be in the first 256 MB of memory, since this is 574 * the maximum mapped by the Linux kernel during initialization. 575 */ 576 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 577 578 /* 579 * Core HID Setup 580 */ 581 #define CONFIG_SYS_HID0_INIT 0x000000000 582 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 583 HID0_ENABLE_INSTRUCTION_CACHE | \ 584 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 585 #define CONFIG_SYS_HID2 HID2_HBE 586 587 /* 588 * MMU Setup 589 */ 590 591 /* DDR: cache cacheable */ 592 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 593 BATL_MEMCOHERENCE) 594 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ 595 BATU_VS | BATU_VP) 596 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 597 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 598 599 /* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */ 600 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 601 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 602 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ 603 BATU_VP) 604 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 605 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 606 607 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 608 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 609 BATL_MEMCOHERENCE) 610 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ 611 BATU_VS | BATU_VP) 612 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 613 BATL_CACHEINHIBIT | \ 614 BATL_GUARDEDSTORAGE) 615 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 616 617 /* Stack in dcache: cacheable, no memory coherence */ 618 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 619 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 620 BATU_VS | BATU_VP) 621 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 622 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 623 624 /* 625 * Environment Configuration 626 */ 627 628 #define CONFIG_ENV_OVERWRITE 629 630 #if defined(CONFIG_TSEC_ENET) 631 #define CONFIG_HAS_ETH0 632 #endif 633 634 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 635 636 637 #define CONFIG_HOSTNAME hrcon 638 #define CONFIG_ROOTPATH "/opt/nfsroot" 639 #define CONFIG_BOOTFILE "uImage" 640 641 #define CONFIG_PREBOOT /* enable preboot variable */ 642 643 #define CONFIG_EXTRA_ENV_SETTINGS \ 644 "netdev=eth0\0" \ 645 "consoledev=ttyS1\0" \ 646 "u-boot=u-boot.bin\0" \ 647 "kernel_addr=1000000\0" \ 648 "fdt_addr=C00000\0" \ 649 "fdtfile=hrcon.dtb\0" \ 650 "load=tftp ${loadaddr} ${u-boot}\0" \ 651 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 652 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ 653 " +${filesize};cp.b ${fileaddr} " \ 654 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 655 "upd=run load update\0" \ 656 657 #define CONFIG_NFSBOOTCOMMAND \ 658 "setenv bootargs root=/dev/nfs rw " \ 659 "nfsroot=$serverip:$rootpath " \ 660 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 661 "console=$consoledev,$baudrate $othbootargs;" \ 662 "tftp ${kernel_addr} $bootfile;" \ 663 "tftp ${fdt_addr} $fdtfile;" \ 664 "bootm ${kernel_addr} - ${fdt_addr}" 665 666 #define CONFIG_MMCBOOTCOMMAND \ 667 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ 668 "console=$consoledev,$baudrate $othbootargs;" \ 669 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \ 670 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \ 671 "bootm ${kernel_addr} - ${fdt_addr}" 672 673 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND 674 675 #endif /* __CONFIG_H */ 676