1 /* 2 * (C) Copyright 2014 3 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc 4 * 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 /* E300 family */ 16 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 17 #define CONFIG_MPC830x 1 /* MPC830x family */ 18 #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ 19 #define CONFIG_STRIDER 1 /* STRIDER board specific */ 20 21 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 22 23 /* 24 * System Clock Setup 25 */ 26 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 27 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 28 29 /* 30 * Hardware Reset Configuration Word 31 * if CLKIN is 66.66MHz, then 32 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz 33 * We choose the A type silicon as default, so the core is 400Mhz. 34 */ 35 #define CONFIG_SYS_HRCW_LOW (\ 36 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 37 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 38 HRCWL_SVCOD_DIV_2 |\ 39 HRCWL_CSB_TO_CLKIN_4X1 |\ 40 HRCWL_CORE_TO_CSB_3X1) 41 /* 42 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits 43 * in 8308's HRCWH according to the manual, but original Freescale's 44 * code has them and I've expirienced some problems using the board 45 * with BDI3000 attached when I've tried to set these bits to zero 46 * (UART doesn't work after the 'reset run' command). 47 */ 48 #define CONFIG_SYS_HRCW_HIGH (\ 49 HRCWH_PCI_HOST |\ 50 HRCWH_PCI1_ARBITER_ENABLE |\ 51 HRCWH_CORE_ENABLE |\ 52 HRCWH_FROM_0XFFF00100 |\ 53 HRCWH_BOOTSEQ_DISABLE |\ 54 HRCWH_SW_WATCHDOG_DISABLE |\ 55 HRCWH_ROM_LOC_LOCAL_16BIT |\ 56 HRCWH_RL_EXT_LEGACY |\ 57 HRCWH_TSEC1M_IN_MII |\ 58 HRCWH_TSEC2M_IN_RGMII |\ 59 HRCWH_BIG_ENDIAN) 60 61 /* 62 * System IO Config 63 */ 64 #define CONFIG_SYS_SICRH (\ 65 SICRH_ESDHC_A_SD |\ 66 SICRH_ESDHC_B_SD |\ 67 SICRH_ESDHC_C_SD |\ 68 SICRH_GPIO_A_GPIO |\ 69 SICRH_GPIO_B_GPIO |\ 70 SICRH_IEEE1588_A_GPIO |\ 71 SICRH_USB |\ 72 SICRH_GTM_GPIO |\ 73 SICRH_IEEE1588_B_GPIO |\ 74 SICRH_ETSEC2_GPIO |\ 75 SICRH_GPIOSEL_1 |\ 76 SICRH_TMROBI_V3P3 |\ 77 SICRH_TSOBI1_V2P5 |\ 78 SICRH_TSOBI2_V2P5) /* 0x0037f103 */ 79 #define CONFIG_SYS_SICRL (\ 80 SICRL_SPI_PF0 |\ 81 SICRL_UART_PF0 |\ 82 SICRL_IRQ_PF0 |\ 83 SICRL_I2C2_PF0 |\ 84 SICRL_ETSEC1_TX_CLK) /* 0x00000000 */ 85 86 /* 87 * IMMR new address 88 */ 89 #define CONFIG_SYS_IMMR 0xE0000000 90 91 /* 92 * SERDES 93 */ 94 #define CONFIG_FSL_SERDES 95 #define CONFIG_FSL_SERDES1 0xe3000 96 97 /* 98 * Arbiter Setup 99 */ 100 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 101 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 102 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 103 104 /* 105 * DDR Setup 106 */ 107 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 108 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 109 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 110 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 111 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 112 | DDRCDR_PZ_LOZ \ 113 | DDRCDR_NZ_LOZ \ 114 | DDRCDR_ODT \ 115 | DDRCDR_Q_DRN) 116 /* 0x7b880001 */ 117 /* 118 * Manually set up DDR parameters 119 * consist of one chip NT5TU64M16HG from NANYA 120 */ 121 122 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 123 124 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 125 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 126 | CSCONFIG_ODT_RD_NEVER \ 127 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 128 | CSCONFIG_BANK_BIT_3 \ 129 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 130 /* 0x80010102 */ 131 #define CONFIG_SYS_DDR_TIMING_3 0 132 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 133 | (0 << TIMING_CFG0_WRT_SHIFT) \ 134 | (0 << TIMING_CFG0_RRT_SHIFT) \ 135 | (0 << TIMING_CFG0_WWT_SHIFT) \ 136 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 137 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 138 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 139 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 140 /* 0x00260802 */ 141 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 142 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 143 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 144 | (7 << TIMING_CFG1_CASLAT_SHIFT) \ 145 | (9 << TIMING_CFG1_REFREC_SHIFT) \ 146 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 147 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 148 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 149 /* 0x26279222 */ 150 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ 151 | (4 << TIMING_CFG2_CPO_SHIFT) \ 152 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 153 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 154 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 155 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 156 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 157 /* 0x021848c5 */ 158 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \ 159 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 160 /* 0x08240100 */ 161 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 162 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 163 | SDRAM_CFG_DBW_16) 164 /* 0x43100000 */ 165 166 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 167 #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ 168 | (0x0242 << SDRAM_MODE_SD_SHIFT)) 169 /* ODT 150ohm CL=4, AL=0 on SDRAM */ 170 #define CONFIG_SYS_DDR_MODE2 0x00000000 171 172 /* 173 * Memory test 174 */ 175 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ 176 #define CONFIG_SYS_MEMTEST_END 0x07f00000 177 178 /* 179 * The reserved memory 180 */ 181 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 182 183 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 184 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 185 186 /* 187 * Initial RAM Base Address Setup 188 */ 189 #define CONFIG_SYS_INIT_RAM_LOCK 1 190 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 191 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 192 #define CONFIG_SYS_GBL_DATA_OFFSET \ 193 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 194 195 /* 196 * Local Bus Configuration & Clock Setup 197 */ 198 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 199 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 200 #define CONFIG_SYS_LBC_LBCR 0x00040000 201 202 /* 203 * FLASH on the Local Bus 204 */ 205 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 206 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 207 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 208 #define CONFIG_FLASH_CFI_LEGACY 209 #define CONFIG_SYS_FLASH_LEGACY_512Kx16 210 211 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 212 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ 213 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 214 215 /* Window base at flash base */ 216 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 217 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 218 219 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 220 | BR_PS_16 /* 16 bit port */ \ 221 | BR_MS_GPCM /* MSEL = GPCM */ \ 222 | BR_V) /* valid */ 223 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 224 | OR_UPM_XAM \ 225 | OR_GPCM_CSNT \ 226 | OR_GPCM_ACS_DIV2 \ 227 | OR_GPCM_XACS \ 228 | OR_GPCM_SCY_15 \ 229 | OR_GPCM_TRLX_SET \ 230 | OR_GPCM_EHTR_SET) 231 232 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 233 #define CONFIG_SYS_MAX_FLASH_SECT 135 234 235 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 236 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 237 238 /* 239 * FPGA 240 */ 241 #define CONFIG_SYS_FPGA0_BASE 0xE0600000 242 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ 243 244 /* Window base at FPGA base */ 245 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE 246 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB) 247 248 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \ 249 | BR_PS_16 /* 16 bit port */ \ 250 | BR_MS_GPCM /* MSEL = GPCM */ \ 251 | BR_V) /* valid */ 252 253 #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \ 254 | OR_UPM_XAM \ 255 | OR_GPCM_CSNT \ 256 | OR_GPCM_SCY_5 \ 257 | OR_GPCM_TRLX_CLEAR \ 258 | OR_GPCM_EHTR_CLEAR) 259 260 #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE 261 #define CONFIG_SYS_FPGA_DONE(k) 0x0010 262 263 #define CONFIG_SYS_FPGA_COUNT 1 264 265 #define CONFIG_SYS_MCLINK_MAX 3 266 267 #define CONFIG_SYS_FPGA_PTR \ 268 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL } 269 270 #define CONFIG_SYS_FPGA_NO_RFL_HI 271 272 /* 273 * Serial Port 274 */ 275 #define CONFIG_SYS_NS16550_SERIAL 276 #define CONFIG_SYS_NS16550_REG_SIZE 1 277 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 278 279 #define CONFIG_SYS_BAUDRATE_TABLE \ 280 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 281 282 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 283 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 284 285 /* Pass open firmware flat tree */ 286 287 /* I2C */ 288 #define CONFIG_SYS_I2C 289 #define CONFIG_SYS_I2C_FSL 290 #define CONFIG_SYS_FSL_I2C_SPEED 400000 291 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 292 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 293 294 #define CONFIG_PCA953X /* NXP PCA9554 */ 295 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x24, 16}, {0x25, 16}, {0x26, 16}, \ 296 {0x3c, 8}, {0x3d, 8}, {0x3e, 8} } 297 298 #define CONFIG_PCA9698 /* NXP PCA9698 */ 299 300 #define CONFIG_SYS_I2C_IHS 301 #define CONFIG_SYS_I2C_IHS_CH0 302 #define CONFIG_SYS_I2C_IHS_SPEED_0 50000 303 #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F 304 #define CONFIG_SYS_I2C_IHS_CH1 305 #define CONFIG_SYS_I2C_IHS_SPEED_1 50000 306 #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F 307 #define CONFIG_SYS_I2C_IHS_CH2 308 #define CONFIG_SYS_I2C_IHS_SPEED_2 50000 309 #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F 310 #define CONFIG_SYS_I2C_IHS_CH3 311 #define CONFIG_SYS_I2C_IHS_SPEED_3 50000 312 #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F 313 314 #ifdef CONFIG_STRIDER_CON_DP 315 #define CONFIG_SYS_I2C_IHS_DUAL 316 #define CONFIG_SYS_I2C_IHS_CH0_1 317 #define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000 318 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F 319 #define CONFIG_SYS_I2C_IHS_CH1_1 320 #define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000 321 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F 322 #define CONFIG_SYS_I2C_IHS_CH2_1 323 #define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000 324 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F 325 #define CONFIG_SYS_I2C_IHS_CH3_1 326 #define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000 327 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F 328 #endif 329 330 /* 331 * Software (bit-bang) I2C driver configuration 332 */ 333 #define CONFIG_SYS_I2C_SOFT 334 #define CONFIG_SOFT_I2C_READ_REPEATED_START 335 #define CONFIG_SYS_I2C_SOFT_SPEED 50000 336 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F 337 #define I2C_SOFT_DECLARATIONS2 338 #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 339 #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F 340 #define I2C_SOFT_DECLARATIONS3 341 #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000 342 #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F 343 #define I2C_SOFT_DECLARATIONS4 344 #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 345 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F 346 #if defined(CONFIG_STRIDER_CON) || defined(CONFIG_STRIDER_CON_DP) 347 #define I2C_SOFT_DECLARATIONS5 348 #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000 349 #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F 350 #define I2C_SOFT_DECLARATIONS6 351 #define CONFIG_SYS_I2C_SOFT_SPEED_6 50000 352 #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F 353 #define I2C_SOFT_DECLARATIONS7 354 #define CONFIG_SYS_I2C_SOFT_SPEED_7 50000 355 #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F 356 #define I2C_SOFT_DECLARATIONS8 357 #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000 358 #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F 359 #endif 360 #ifdef CONFIG_STRIDER_CON_DP 361 #define I2C_SOFT_DECLARATIONS9 362 #define CONFIG_SYS_I2C_SOFT_SPEED_9 50000 363 #define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F 364 #define I2C_SOFT_DECLARATIONS10 365 #define CONFIG_SYS_I2C_SOFT_SPEED_10 50000 366 #define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F 367 #define I2C_SOFT_DECLARATIONS11 368 #define CONFIG_SYS_I2C_SOFT_SPEED_11 50000 369 #define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F 370 #define I2C_SOFT_DECLARATIONS12 371 #define CONFIG_SYS_I2C_SOFT_SPEED_12 50000 372 #define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F 373 #endif 374 375 #ifdef CONFIG_STRIDER_CON 376 #define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8} 377 #define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8} 378 #define CONFIG_SYS_ADV7611_I2C {5, 6, 7, 8} 379 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 380 #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \ 381 {12, 0x4c} } 382 #elif defined(CONFIG_STRIDER_CON_DP) 383 #define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20} 384 #define CONFIG_SYS_CH7301_I2C {1, 3, 5, 7} 385 #define CONFIG_SYS_ADV7611_I2C {1, 3, 5, 7} 386 #define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8} 387 #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \ 388 {12, 0x4c} } 389 #elif defined(CONFIG_STRIDER_CPU_DP) 390 #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4} 391 #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4} 392 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 393 #define CONFIG_STRIDER_FANS { {6, 0x4c}, {7, 0x4c}, \ 394 {8, 0x4c} } 395 #else 396 #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4} 397 #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4} 398 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 399 #define CONFIG_STRIDER_FANS { {2, 0x18}, {3, 0x18}, \ 400 {4, 0x18} } 401 #endif 402 403 #ifndef __ASSEMBLY__ 404 void fpga_gpio_set(unsigned int bus, int pin); 405 void fpga_gpio_clear(unsigned int bus, int pin); 406 int fpga_gpio_get(unsigned int bus, int pin); 407 void fpga_control_set(unsigned int bus, int pin); 408 void fpga_control_clear(unsigned int bus, int pin); 409 #endif 410 411 #ifdef CONFIG_STRIDER_CON 412 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040) 413 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020) 414 #define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \ 415 (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR) 416 #elif defined(CONFIG_STRIDER_CON_DP) 417 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200) 418 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100) 419 #define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4) 420 #else 421 #define I2C_SDA_GPIO 0x0040 422 #define I2C_SCL_GPIO 0x0020 423 #define I2C_FPGA_IDX I2C_ADAP_HWNR 424 #endif 425 426 #ifdef CONFIG_STRIDER_CON_DP 427 #define I2C_ACTIVE \ 428 do { \ 429 if (I2C_ADAP_HWNR > 7) \ 430 fpga_control_set(I2C_FPGA_IDX, 0x0004); \ 431 else \ 432 fpga_control_clear(I2C_FPGA_IDX, 0x0004); \ 433 } while (0) 434 #else 435 #define I2C_ACTIVE { } 436 #endif 437 438 #define I2C_TRISTATE { } 439 #define I2C_READ \ 440 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0) 441 #define I2C_SDA(bit) \ 442 do { \ 443 if (bit) \ 444 fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \ 445 else \ 446 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \ 447 } while (0) 448 #define I2C_SCL(bit) \ 449 do { \ 450 if (bit) \ 451 fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \ 452 else \ 453 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \ 454 } while (0) 455 #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ 456 457 /* 458 * Software (bit-bang) MII driver configuration 459 */ 460 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 461 #define CONFIG_BITBANGMII_MULTI 462 463 /* 464 * OSD Setup 465 */ 466 #define CONFIG_SYS_OSD_SCREENS 1 467 #define CONFIG_SYS_DP501_DIFFERENTIAL 468 #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ 469 470 #ifdef CONFIG_STRIDER_CON_DP 471 #define CONFIG_SYS_OSD_DH 472 #endif 473 474 /* 475 * General PCI 476 * Addresses are mapped 1-1. 477 */ 478 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 479 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 480 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 481 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 482 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 483 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 484 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 485 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 486 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 487 488 /* enable PCIE clock */ 489 #define CONFIG_SYS_SCCR_PCIEXP1CM 1 490 491 #define CONFIG_PCI_INDIRECT_BRIDGE 492 #define CONFIG_PCIE 493 494 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 495 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 496 497 /* 498 * TSEC 499 */ 500 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 501 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 502 503 /* 504 * TSEC ethernet configuration 505 */ 506 #define CONFIG_MII 1 /* MII PHY management */ 507 #define CONFIG_TSEC1 508 #define CONFIG_TSEC1_NAME "eTSEC0" 509 #define TSEC1_PHY_ADDR 1 510 #define TSEC1_PHYIDX 0 511 #define TSEC1_FLAGS 0 512 513 /* Options are: eTSEC[0-1] */ 514 #define CONFIG_ETHPRIME "eTSEC0" 515 516 /* 517 * Environment 518 */ 519 #if 1 520 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 521 CONFIG_SYS_MONITOR_LEN) 522 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 523 #define CONFIG_ENV_SIZE 0x2000 524 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 525 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 526 #else 527 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 528 #endif 529 530 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 531 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 532 533 /* 534 * Command line configuration. 535 */ 536 537 /* 538 * Miscellaneous configurable options 539 */ 540 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 541 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 542 543 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 544 545 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 546 547 /* 548 * For booting Linux, the board info and command line data 549 * have to be in the first 256 MB of memory, since this is 550 * the maximum mapped by the Linux kernel during initialization. 551 */ 552 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 553 554 /* 555 * Core HID Setup 556 */ 557 #define CONFIG_SYS_HID0_INIT 0x000000000 558 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 559 HID0_ENABLE_INSTRUCTION_CACHE | \ 560 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 561 #define CONFIG_SYS_HID2 HID2_HBE 562 563 /* 564 * MMU Setup 565 */ 566 567 /* DDR: cache cacheable */ 568 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 569 BATL_MEMCOHERENCE) 570 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ 571 BATU_VS | BATU_VP) 572 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 573 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 574 575 /* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */ 576 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 577 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 578 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ 579 BATU_VP) 580 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 581 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 582 583 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 584 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 585 BATL_MEMCOHERENCE) 586 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ 587 BATU_VS | BATU_VP) 588 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 589 BATL_CACHEINHIBIT | \ 590 BATL_GUARDEDSTORAGE) 591 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 592 593 /* Stack in dcache: cacheable, no memory coherence */ 594 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 595 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 596 BATU_VS | BATU_VP) 597 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 598 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 599 600 /* 601 * Environment Configuration 602 */ 603 604 #define CONFIG_ENV_OVERWRITE 605 606 #if defined(CONFIG_TSEC_ENET) 607 #define CONFIG_HAS_ETH0 608 #endif 609 610 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 611 612 613 #define CONFIG_HOSTNAME "hrcon" 614 #define CONFIG_ROOTPATH "/opt/nfsroot" 615 #define CONFIG_BOOTFILE "uImage" 616 617 #define CONFIG_PREBOOT /* enable preboot variable */ 618 619 #define CONFIG_EXTRA_ENV_SETTINGS \ 620 "netdev=eth0\0" \ 621 "consoledev=ttyS1\0" \ 622 "u-boot=u-boot.bin\0" \ 623 "kernel_addr=1000000\0" \ 624 "fdt_addr=C00000\0" \ 625 "fdtfile=hrcon.dtb\0" \ 626 "load=tftp ${loadaddr} ${u-boot}\0" \ 627 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 628 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ 629 " +${filesize};cp.b ${fileaddr} " \ 630 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 631 "upd=run load update\0" \ 632 633 #define CONFIG_NFSBOOTCOMMAND \ 634 "setenv bootargs root=/dev/nfs rw " \ 635 "nfsroot=$serverip:$rootpath " \ 636 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 637 "console=$consoledev,$baudrate $othbootargs;" \ 638 "tftp ${kernel_addr} $bootfile;" \ 639 "tftp ${fdt_addr} $fdtfile;" \ 640 "bootm ${kernel_addr} - ${fdt_addr}" 641 642 #define CONFIG_MMCBOOTCOMMAND \ 643 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ 644 "console=$consoledev,$baudrate $othbootargs;" \ 645 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \ 646 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \ 647 "bootm ${kernel_addr} - ${fdt_addr}" 648 649 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND 650 651 #endif /* __CONFIG_H */ 652