1 /* 2 * (C) Copyright 2014 3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de 4 * 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 /* E300 family */ 16 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 17 #define CONFIG_MPC830x 1 /* MPC830x family */ 18 #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ 19 #define CONFIG_STRIDER 1 /* STRIDER board specific */ 20 21 #define CONFIG_SYS_TEXT_BASE 0xFE000000 22 23 #define CONFIG_BOARD_EARLY_INIT_F 24 #define CONFIG_BOARD_EARLY_INIT_R 25 #define CONFIG_LAST_STAGE_INIT 26 27 #define CONFIG_FSL_ESDHC 28 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 29 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 30 31 #define CONFIG_GENERIC_MMC 32 #define CONFIG_DOS_PARTITION 33 34 #define CONFIG_SYS_ALT_MEMTEST 35 36 #define CONFIG_CMD_FPGAD 37 #define CONFIG_CMD_IOLOOP 38 39 /* 40 * System Clock Setup 41 */ 42 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 43 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 44 45 /* 46 * Hardware Reset Configuration Word 47 * if CLKIN is 66.66MHz, then 48 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz 49 * We choose the A type silicon as default, so the core is 400Mhz. 50 */ 51 #define CONFIG_SYS_HRCW_LOW (\ 52 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 53 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 54 HRCWL_SVCOD_DIV_2 |\ 55 HRCWL_CSB_TO_CLKIN_4X1 |\ 56 HRCWL_CORE_TO_CSB_3X1) 57 /* 58 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits 59 * in 8308's HRCWH according to the manual, but original Freescale's 60 * code has them and I've expirienced some problems using the board 61 * with BDI3000 attached when I've tried to set these bits to zero 62 * (UART doesn't work after the 'reset run' command). 63 */ 64 #define CONFIG_SYS_HRCW_HIGH (\ 65 HRCWH_PCI_HOST |\ 66 HRCWH_PCI1_ARBITER_ENABLE |\ 67 HRCWH_CORE_ENABLE |\ 68 HRCWH_FROM_0XFFF00100 |\ 69 HRCWH_BOOTSEQ_DISABLE |\ 70 HRCWH_SW_WATCHDOG_DISABLE |\ 71 HRCWH_ROM_LOC_LOCAL_16BIT |\ 72 HRCWH_RL_EXT_LEGACY |\ 73 HRCWH_TSEC1M_IN_MII |\ 74 HRCWH_TSEC2M_IN_RGMII |\ 75 HRCWH_BIG_ENDIAN) 76 77 /* 78 * System IO Config 79 */ 80 #define CONFIG_SYS_SICRH (\ 81 SICRH_ESDHC_A_SD |\ 82 SICRH_ESDHC_B_SD |\ 83 SICRH_ESDHC_C_SD |\ 84 SICRH_GPIO_A_GPIO |\ 85 SICRH_GPIO_B_GPIO |\ 86 SICRH_IEEE1588_A_GPIO |\ 87 SICRH_USB |\ 88 SICRH_GTM_GPIO |\ 89 SICRH_IEEE1588_B_GPIO |\ 90 SICRH_ETSEC2_GPIO |\ 91 SICRH_GPIOSEL_1 |\ 92 SICRH_TMROBI_V3P3 |\ 93 SICRH_TSOBI1_V2P5 |\ 94 SICRH_TSOBI2_V2P5) /* 0x0037f103 */ 95 #define CONFIG_SYS_SICRL (\ 96 SICRL_SPI_PF0 |\ 97 SICRL_UART_PF0 |\ 98 SICRL_IRQ_PF0 |\ 99 SICRL_I2C2_PF0 |\ 100 SICRL_ETSEC1_TX_CLK) /* 0x00000000 */ 101 102 /* 103 * IMMR new address 104 */ 105 #define CONFIG_SYS_IMMR 0xE0000000 106 107 /* 108 * SERDES 109 */ 110 #define CONFIG_FSL_SERDES 111 #define CONFIG_FSL_SERDES1 0xe3000 112 113 /* 114 * Arbiter Setup 115 */ 116 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 117 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 118 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 119 120 /* 121 * DDR Setup 122 */ 123 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 124 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 125 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 126 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 127 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 128 | DDRCDR_PZ_LOZ \ 129 | DDRCDR_NZ_LOZ \ 130 | DDRCDR_ODT \ 131 | DDRCDR_Q_DRN) 132 /* 0x7b880001 */ 133 /* 134 * Manually set up DDR parameters 135 * consist of one chip NT5TU64M16HG from NANYA 136 */ 137 138 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 139 140 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 141 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 142 | CSCONFIG_ODT_RD_NEVER \ 143 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 144 | CSCONFIG_BANK_BIT_3 \ 145 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 146 /* 0x80010102 */ 147 #define CONFIG_SYS_DDR_TIMING_3 0 148 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 149 | (0 << TIMING_CFG0_WRT_SHIFT) \ 150 | (0 << TIMING_CFG0_RRT_SHIFT) \ 151 | (0 << TIMING_CFG0_WWT_SHIFT) \ 152 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 153 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 154 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 155 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 156 /* 0x00260802 */ 157 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 158 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 159 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 160 | (7 << TIMING_CFG1_CASLAT_SHIFT) \ 161 | (9 << TIMING_CFG1_REFREC_SHIFT) \ 162 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 163 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 164 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 165 /* 0x26279222 */ 166 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ 167 | (4 << TIMING_CFG2_CPO_SHIFT) \ 168 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 169 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 170 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 171 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 172 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 173 /* 0x021848c5 */ 174 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \ 175 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 176 /* 0x08240100 */ 177 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 178 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 179 | SDRAM_CFG_DBW_16) 180 /* 0x43100000 */ 181 182 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 183 #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ 184 | (0x0242 << SDRAM_MODE_SD_SHIFT)) 185 /* ODT 150ohm CL=4, AL=0 on SDRAM */ 186 #define CONFIG_SYS_DDR_MODE2 0x00000000 187 188 /* 189 * Memory test 190 */ 191 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ 192 #define CONFIG_SYS_MEMTEST_END 0x07f00000 193 194 /* 195 * The reserved memory 196 */ 197 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 198 199 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 200 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 201 202 /* 203 * Initial RAM Base Address Setup 204 */ 205 #define CONFIG_SYS_INIT_RAM_LOCK 1 206 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 207 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 208 #define CONFIG_SYS_GBL_DATA_OFFSET \ 209 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 210 211 /* 212 * Local Bus Configuration & Clock Setup 213 */ 214 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 215 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 216 #define CONFIG_SYS_LBC_LBCR 0x00040000 217 218 /* 219 * FLASH on the Local Bus 220 */ 221 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 222 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 223 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 224 #define CONFIG_FLASH_CFI_LEGACY 225 #define CONFIG_SYS_FLASH_LEGACY_512Kx16 226 227 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 228 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ 229 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 230 231 /* Window base at flash base */ 232 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 233 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 234 235 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 236 | BR_PS_16 /* 16 bit port */ \ 237 | BR_MS_GPCM /* MSEL = GPCM */ \ 238 | BR_V) /* valid */ 239 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 240 | OR_UPM_XAM \ 241 | OR_GPCM_CSNT \ 242 | OR_GPCM_ACS_DIV2 \ 243 | OR_GPCM_XACS \ 244 | OR_GPCM_SCY_15 \ 245 | OR_GPCM_TRLX_SET \ 246 | OR_GPCM_EHTR_SET) 247 248 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 249 #define CONFIG_SYS_MAX_FLASH_SECT 135 250 251 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 252 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 253 254 /* 255 * FPGA 256 */ 257 #define CONFIG_SYS_FPGA0_BASE 0xE0600000 258 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ 259 260 /* Window base at FPGA base */ 261 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE 262 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB) 263 264 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \ 265 | BR_PS_16 /* 16 bit port */ \ 266 | BR_MS_GPCM /* MSEL = GPCM */ \ 267 | BR_V) /* valid */ 268 269 #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \ 270 | OR_UPM_XAM \ 271 | OR_GPCM_CSNT \ 272 | OR_GPCM_SCY_5 \ 273 | OR_GPCM_TRLX_CLEAR \ 274 | OR_GPCM_EHTR_CLEAR) 275 276 #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE 277 #define CONFIG_SYS_FPGA_DONE(k) 0x0010 278 279 #define CONFIG_SYS_FPGA_COUNT 1 280 281 #define CONFIG_SYS_MCLINK_MAX 3 282 283 #define CONFIG_SYS_FPGA_PTR \ 284 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL } 285 286 #define CONFIG_SYS_FPGA_NO_RFL_HI 287 288 /* 289 * Serial Port 290 */ 291 #define CONFIG_CONS_INDEX 2 292 #define CONFIG_SYS_NS16550_SERIAL 293 #define CONFIG_SYS_NS16550_REG_SIZE 1 294 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 295 296 #define CONFIG_SYS_BAUDRATE_TABLE \ 297 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 298 299 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 300 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 301 302 /* Pass open firmware flat tree */ 303 304 /* I2C */ 305 #define CONFIG_SYS_I2C 306 #define CONFIG_SYS_I2C_FSL 307 #define CONFIG_SYS_FSL_I2C_SPEED 400000 308 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 309 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 310 311 #define CONFIG_PCA953X /* NXP PCA9554 */ 312 #define CONFIG_CMD_PCA953X 313 #define CONFIG_CMD_PCA953X_INFO 314 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x24, 16}, {0x25, 16}, {0x26, 16}, \ 315 {0x3c, 8}, {0x3d, 8}, {0x3e, 8} } 316 317 #define CONFIG_PCA9698 /* NXP PCA9698 */ 318 319 #define CONFIG_SYS_I2C_IHS 320 #define CONFIG_SYS_I2C_IHS_CH0 321 #define CONFIG_SYS_I2C_IHS_SPEED_0 50000 322 #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F 323 #define CONFIG_SYS_I2C_IHS_CH1 324 #define CONFIG_SYS_I2C_IHS_SPEED_1 50000 325 #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F 326 #define CONFIG_SYS_I2C_IHS_CH2 327 #define CONFIG_SYS_I2C_IHS_SPEED_2 50000 328 #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F 329 #define CONFIG_SYS_I2C_IHS_CH3 330 #define CONFIG_SYS_I2C_IHS_SPEED_3 50000 331 #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F 332 333 #ifdef CONFIG_STRIDER_CON_DP 334 #define CONFIG_SYS_I2C_IHS_DUAL 335 #define CONFIG_SYS_I2C_IHS_CH0_1 336 #define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000 337 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F 338 #define CONFIG_SYS_I2C_IHS_CH1_1 339 #define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000 340 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F 341 #define CONFIG_SYS_I2C_IHS_CH2_1 342 #define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000 343 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F 344 #define CONFIG_SYS_I2C_IHS_CH3_1 345 #define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000 346 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F 347 #endif 348 349 /* 350 * Software (bit-bang) I2C driver configuration 351 */ 352 #define CONFIG_SYS_I2C_SOFT 353 #define CONFIG_SOFT_I2C_READ_REPEATED_START 354 #define CONFIG_SYS_I2C_SOFT_SPEED 50000 355 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F 356 #define I2C_SOFT_DECLARATIONS2 357 #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 358 #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F 359 #define I2C_SOFT_DECLARATIONS3 360 #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000 361 #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F 362 #define I2C_SOFT_DECLARATIONS4 363 #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 364 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F 365 #if defined(CONFIG_STRIDER_CON) || defined(CONFIG_STRIDER_CON_DP) 366 #define I2C_SOFT_DECLARATIONS5 367 #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000 368 #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F 369 #define I2C_SOFT_DECLARATIONS6 370 #define CONFIG_SYS_I2C_SOFT_SPEED_6 50000 371 #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F 372 #define I2C_SOFT_DECLARATIONS7 373 #define CONFIG_SYS_I2C_SOFT_SPEED_7 50000 374 #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F 375 #define I2C_SOFT_DECLARATIONS8 376 #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000 377 #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F 378 #endif 379 #ifdef CONFIG_STRIDER_CON_DP 380 #define I2C_SOFT_DECLARATIONS9 381 #define CONFIG_SYS_I2C_SOFT_SPEED_9 50000 382 #define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F 383 #define I2C_SOFT_DECLARATIONS10 384 #define CONFIG_SYS_I2C_SOFT_SPEED_10 50000 385 #define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F 386 #define I2C_SOFT_DECLARATIONS11 387 #define CONFIG_SYS_I2C_SOFT_SPEED_11 50000 388 #define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F 389 #define I2C_SOFT_DECLARATIONS12 390 #define CONFIG_SYS_I2C_SOFT_SPEED_12 50000 391 #define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F 392 #endif 393 394 #ifdef CONFIG_STRIDER_CON 395 #define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8} 396 #define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8} 397 #define CONFIG_SYS_ADV7611_I2C {5, 6, 7, 8} 398 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 399 #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \ 400 {12, 0x4c} } 401 #elif defined(CONFIG_STRIDER_CON_DP) 402 #define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20} 403 #define CONFIG_SYS_CH7301_I2C {1, 3, 5, 7} 404 #define CONFIG_SYS_ADV7611_I2C {1, 3, 5, 7} 405 #define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8} 406 #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \ 407 {12, 0x4c} } 408 #elif defined(CONFIG_STRIDER_CPU_DP) 409 #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4} 410 #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4} 411 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 412 #define CONFIG_STRIDER_FANS { {6, 0x4c}, {7, 0x4c}, \ 413 {8, 0x4c} } 414 #else 415 #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4} 416 #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4} 417 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 418 #define CONFIG_STRIDER_FANS { {2, 0x18}, {3, 0x18}, \ 419 {4, 0x18} } 420 #endif 421 422 #ifndef __ASSEMBLY__ 423 void fpga_gpio_set(unsigned int bus, int pin); 424 void fpga_gpio_clear(unsigned int bus, int pin); 425 int fpga_gpio_get(unsigned int bus, int pin); 426 void fpga_control_set(unsigned int bus, int pin); 427 void fpga_control_clear(unsigned int bus, int pin); 428 #endif 429 430 #ifdef CONFIG_STRIDER_CON 431 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040) 432 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020) 433 #define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \ 434 (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR) 435 #elif defined(CONFIG_STRIDER_CON_DP) 436 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200) 437 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100) 438 #define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4) 439 #else 440 #define I2C_SDA_GPIO 0x0040 441 #define I2C_SCL_GPIO 0x0020 442 #define I2C_FPGA_IDX I2C_ADAP_HWNR 443 #endif 444 445 #ifdef CONFIG_STRIDER_CON_DP 446 #define I2C_ACTIVE \ 447 do { \ 448 if (I2C_ADAP_HWNR > 7) \ 449 fpga_control_set(I2C_FPGA_IDX, 0x0004); \ 450 else \ 451 fpga_control_clear(I2C_FPGA_IDX, 0x0004); \ 452 } while (0) 453 #else 454 #define I2C_ACTIVE { } 455 #endif 456 457 #define I2C_TRISTATE { } 458 #define I2C_READ \ 459 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0) 460 #define I2C_SDA(bit) \ 461 do { \ 462 if (bit) \ 463 fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \ 464 else \ 465 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \ 466 } while (0) 467 #define I2C_SCL(bit) \ 468 do { \ 469 if (bit) \ 470 fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \ 471 else \ 472 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \ 473 } while (0) 474 #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ 475 476 /* 477 * Software (bit-bang) MII driver configuration 478 */ 479 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 480 #define CONFIG_BITBANGMII_MULTI 481 482 /* 483 * OSD Setup 484 */ 485 #define CONFIG_SYS_OSD_SCREENS 1 486 #define CONFIG_SYS_DP501_DIFFERENTIAL 487 #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ 488 489 #ifdef CONFIG_STRIDER_CON_DP 490 #define CONFIG_SYS_OSD_DH 491 #endif 492 493 /* 494 * General PCI 495 * Addresses are mapped 1-1. 496 */ 497 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 498 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 499 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 500 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 501 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 502 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 503 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 504 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 505 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 506 507 /* enable PCIE clock */ 508 #define CONFIG_SYS_SCCR_PCIEXP1CM 1 509 510 #define CONFIG_PCI_INDIRECT_BRIDGE 511 #define CONFIG_PCIE 512 513 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 514 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 515 516 /* 517 * TSEC 518 */ 519 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 520 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 521 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 522 523 /* 524 * TSEC ethernet configuration 525 */ 526 #define CONFIG_MII 1 /* MII PHY management */ 527 #define CONFIG_TSEC1 528 #define CONFIG_TSEC1_NAME "eTSEC0" 529 #define TSEC1_PHY_ADDR 1 530 #define TSEC1_PHYIDX 0 531 #define TSEC1_FLAGS 0 532 533 /* Options are: eTSEC[0-1] */ 534 #define CONFIG_ETHPRIME "eTSEC0" 535 536 /* 537 * Environment 538 */ 539 #if 1 540 #define CONFIG_ENV_IS_IN_FLASH 1 541 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 542 CONFIG_SYS_MONITOR_LEN) 543 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 544 #define CONFIG_ENV_SIZE 0x2000 545 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 546 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 547 #else 548 #define CONFIG_ENV_IS_NOWHERE 549 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 550 #endif 551 552 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 553 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 554 555 /* 556 * Command line configuration. 557 */ 558 #define CONFIG_CMD_PCI 559 560 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 561 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 562 563 /* 564 * Miscellaneous configurable options 565 */ 566 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 567 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 568 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 569 570 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 571 572 /* Print Buffer Size */ 573 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 574 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 575 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 576 577 /* 578 * For booting Linux, the board info and command line data 579 * have to be in the first 256 MB of memory, since this is 580 * the maximum mapped by the Linux kernel during initialization. 581 */ 582 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 583 584 /* 585 * Core HID Setup 586 */ 587 #define CONFIG_SYS_HID0_INIT 0x000000000 588 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 589 HID0_ENABLE_INSTRUCTION_CACHE | \ 590 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 591 #define CONFIG_SYS_HID2 HID2_HBE 592 593 /* 594 * MMU Setup 595 */ 596 597 /* DDR: cache cacheable */ 598 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 599 BATL_MEMCOHERENCE) 600 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ 601 BATU_VS | BATU_VP) 602 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 603 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 604 605 /* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */ 606 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 607 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 608 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ 609 BATU_VP) 610 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 611 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 612 613 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 614 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 615 BATL_MEMCOHERENCE) 616 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ 617 BATU_VS | BATU_VP) 618 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 619 BATL_CACHEINHIBIT | \ 620 BATL_GUARDEDSTORAGE) 621 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 622 623 /* Stack in dcache: cacheable, no memory coherence */ 624 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 625 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 626 BATU_VS | BATU_VP) 627 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 628 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 629 630 /* 631 * Environment Configuration 632 */ 633 634 #define CONFIG_ENV_OVERWRITE 635 636 #if defined(CONFIG_TSEC_ENET) 637 #define CONFIG_HAS_ETH0 638 #endif 639 640 #define CONFIG_BAUDRATE 115200 641 642 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 643 644 645 #define CONFIG_HOSTNAME hrcon 646 #define CONFIG_ROOTPATH "/opt/nfsroot" 647 #define CONFIG_BOOTFILE "uImage" 648 649 #define CONFIG_PREBOOT /* enable preboot variable */ 650 651 #define CONFIG_EXTRA_ENV_SETTINGS \ 652 "netdev=eth0\0" \ 653 "consoledev=ttyS1\0" \ 654 "u-boot=u-boot.bin\0" \ 655 "kernel_addr=1000000\0" \ 656 "fdt_addr=C00000\0" \ 657 "fdtfile=hrcon.dtb\0" \ 658 "load=tftp ${loadaddr} ${u-boot}\0" \ 659 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 660 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ 661 " +${filesize};cp.b ${fileaddr} " \ 662 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 663 "upd=run load update\0" \ 664 665 #define CONFIG_NFSBOOTCOMMAND \ 666 "setenv bootargs root=/dev/nfs rw " \ 667 "nfsroot=$serverip:$rootpath " \ 668 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 669 "console=$consoledev,$baudrate $othbootargs;" \ 670 "tftp ${kernel_addr} $bootfile;" \ 671 "tftp ${fdt_addr} $fdtfile;" \ 672 "bootm ${kernel_addr} - ${fdt_addr}" 673 674 #define CONFIG_MMCBOOTCOMMAND \ 675 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ 676 "console=$consoledev,$baudrate $othbootargs;" \ 677 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \ 678 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \ 679 "bootm ${kernel_addr} - ${fdt_addr}" 680 681 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND 682 683 #endif /* __CONFIG_H */ 684