1 /* 2 * (C) Copyright 2014 3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de 4 * 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 /* E300 family */ 16 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 17 #define CONFIG_MPC830x 1 /* MPC830x family */ 18 #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ 19 #define CONFIG_STRIDER 1 /* STRIDER board specific */ 20 21 #define CONFIG_SYS_TEXT_BASE 0xFE000000 22 23 #ifdef CONFIG_STRIDER_CPU 24 #define CONFIG_IDENT_STRING " strider cpu 0.01" 25 #else 26 #define CONFIG_IDENT_STRING " strider con 0.01" 27 #endif 28 29 #define CONFIG_BOARD_EARLY_INIT_F 30 #define CONFIG_BOARD_EARLY_INIT_R 31 #define CONFIG_LAST_STAGE_INIT 32 33 #define CONFIG_MMC 34 #define CONFIG_FSL_ESDHC 35 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 36 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 37 38 #define CONFIG_GENERIC_MMC 39 #define CONFIG_DOS_PARTITION 40 41 #define CONFIG_SYS_ALT_MEMTEST 42 43 #define CONFIG_CMD_FPGAD 44 #define CONFIG_CMD_IOLOOP 45 46 /* 47 * System Clock Setup 48 */ 49 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 50 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 51 52 /* 53 * Hardware Reset Configuration Word 54 * if CLKIN is 66.66MHz, then 55 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz 56 * We choose the A type silicon as default, so the core is 400Mhz. 57 */ 58 #define CONFIG_SYS_HRCW_LOW (\ 59 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 60 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 61 HRCWL_SVCOD_DIV_2 |\ 62 HRCWL_CSB_TO_CLKIN_4X1 |\ 63 HRCWL_CORE_TO_CSB_3X1) 64 /* 65 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits 66 * in 8308's HRCWH according to the manual, but original Freescale's 67 * code has them and I've expirienced some problems using the board 68 * with BDI3000 attached when I've tried to set these bits to zero 69 * (UART doesn't work after the 'reset run' command). 70 */ 71 #define CONFIG_SYS_HRCW_HIGH (\ 72 HRCWH_PCI_HOST |\ 73 HRCWH_PCI1_ARBITER_ENABLE |\ 74 HRCWH_CORE_ENABLE |\ 75 HRCWH_FROM_0XFFF00100 |\ 76 HRCWH_BOOTSEQ_DISABLE |\ 77 HRCWH_SW_WATCHDOG_DISABLE |\ 78 HRCWH_ROM_LOC_LOCAL_16BIT |\ 79 HRCWH_RL_EXT_LEGACY |\ 80 HRCWH_TSEC1M_IN_MII |\ 81 HRCWH_TSEC2M_IN_RGMII |\ 82 HRCWH_BIG_ENDIAN) 83 84 /* 85 * System IO Config 86 */ 87 #define CONFIG_SYS_SICRH (\ 88 SICRH_ESDHC_A_SD |\ 89 SICRH_ESDHC_B_SD |\ 90 SICRH_ESDHC_C_SD |\ 91 SICRH_GPIO_A_GPIO |\ 92 SICRH_GPIO_B_GPIO |\ 93 SICRH_IEEE1588_A_GPIO |\ 94 SICRH_USB |\ 95 SICRH_GTM_GPIO |\ 96 SICRH_IEEE1588_B_GPIO |\ 97 SICRH_ETSEC2_GPIO |\ 98 SICRH_GPIOSEL_1 |\ 99 SICRH_TMROBI_V3P3 |\ 100 SICRH_TSOBI1_V2P5 |\ 101 SICRH_TSOBI2_V2P5) /* 0x0037f103 */ 102 #define CONFIG_SYS_SICRL (\ 103 SICRL_SPI_PF0 |\ 104 SICRL_UART_PF0 |\ 105 SICRL_IRQ_PF0 |\ 106 SICRL_I2C2_PF0 |\ 107 SICRL_ETSEC1_TX_CLK) /* 0x00000000 */ 108 109 /* 110 * IMMR new address 111 */ 112 #define CONFIG_SYS_IMMR 0xE0000000 113 114 /* 115 * SERDES 116 */ 117 #define CONFIG_FSL_SERDES 118 #define CONFIG_FSL_SERDES1 0xe3000 119 120 /* 121 * Arbiter Setup 122 */ 123 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 124 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 125 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 126 127 /* 128 * DDR Setup 129 */ 130 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 131 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 132 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 133 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 134 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 135 | DDRCDR_PZ_LOZ \ 136 | DDRCDR_NZ_LOZ \ 137 | DDRCDR_ODT \ 138 | DDRCDR_Q_DRN) 139 /* 0x7b880001 */ 140 /* 141 * Manually set up DDR parameters 142 * consist of one chip NT5TU64M16HG from NANYA 143 */ 144 145 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 146 147 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 148 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 149 | CSCONFIG_ODT_RD_NEVER \ 150 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 151 | CSCONFIG_BANK_BIT_3 \ 152 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 153 /* 0x80010102 */ 154 #define CONFIG_SYS_DDR_TIMING_3 0 155 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 156 | (0 << TIMING_CFG0_WRT_SHIFT) \ 157 | (0 << TIMING_CFG0_RRT_SHIFT) \ 158 | (0 << TIMING_CFG0_WWT_SHIFT) \ 159 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 160 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 161 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 162 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 163 /* 0x00260802 */ 164 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 165 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 166 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 167 | (7 << TIMING_CFG1_CASLAT_SHIFT) \ 168 | (9 << TIMING_CFG1_REFREC_SHIFT) \ 169 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 170 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 171 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 172 /* 0x26279222 */ 173 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ 174 | (4 << TIMING_CFG2_CPO_SHIFT) \ 175 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 176 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 177 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 178 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 179 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 180 /* 0x021848c5 */ 181 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \ 182 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 183 /* 0x08240100 */ 184 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 185 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 186 | SDRAM_CFG_DBW_16) 187 /* 0x43100000 */ 188 189 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 190 #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ 191 | (0x0242 << SDRAM_MODE_SD_SHIFT)) 192 /* ODT 150ohm CL=4, AL=0 on SDRAM */ 193 #define CONFIG_SYS_DDR_MODE2 0x00000000 194 195 /* 196 * Memory test 197 */ 198 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ 199 #define CONFIG_SYS_MEMTEST_END 0x07f00000 200 201 /* 202 * The reserved memory 203 */ 204 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 205 206 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 207 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 208 209 /* 210 * Initial RAM Base Address Setup 211 */ 212 #define CONFIG_SYS_INIT_RAM_LOCK 1 213 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 214 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 215 #define CONFIG_SYS_GBL_DATA_OFFSET \ 216 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 217 218 /* 219 * Local Bus Configuration & Clock Setup 220 */ 221 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 222 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 223 #define CONFIG_SYS_LBC_LBCR 0x00040000 224 225 /* 226 * FLASH on the Local Bus 227 */ 228 #if 1 229 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 230 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 231 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 232 #define CONFIG_FLASH_CFI_LEGACY 233 #define CONFIG_SYS_FLASH_LEGACY_512Kx16 234 #else 235 #define CONFIG_SYS_NO_FLASH 236 #endif 237 238 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 239 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ 240 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 241 242 /* Window base at flash base */ 243 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 244 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 245 246 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 247 | BR_PS_16 /* 16 bit port */ \ 248 | BR_MS_GPCM /* MSEL = GPCM */ \ 249 | BR_V) /* valid */ 250 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 251 | OR_UPM_XAM \ 252 | OR_GPCM_CSNT \ 253 | OR_GPCM_ACS_DIV2 \ 254 | OR_GPCM_XACS \ 255 | OR_GPCM_SCY_15 \ 256 | OR_GPCM_TRLX_SET \ 257 | OR_GPCM_EHTR_SET) 258 259 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 260 #define CONFIG_SYS_MAX_FLASH_SECT 135 261 262 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 263 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 264 265 /* 266 * FPGA 267 */ 268 #define CONFIG_SYS_FPGA0_BASE 0xE0600000 269 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ 270 271 /* Window base at FPGA base */ 272 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE 273 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB) 274 275 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \ 276 | BR_PS_16 /* 16 bit port */ \ 277 | BR_MS_GPCM /* MSEL = GPCM */ \ 278 | BR_V) /* valid */ 279 280 #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \ 281 | OR_UPM_XAM \ 282 | OR_GPCM_CSNT \ 283 | OR_GPCM_SCY_5 \ 284 | OR_GPCM_TRLX_CLEAR \ 285 | OR_GPCM_EHTR_CLEAR) 286 287 #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE 288 #define CONFIG_SYS_FPGA_DONE(k) 0x0010 289 290 #define CONFIG_SYS_FPGA_COUNT 1 291 292 #define CONFIG_SYS_MCLINK_MAX 3 293 294 #define CONFIG_SYS_FPGA_PTR \ 295 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL } 296 297 #define CONFIG_SYS_FPGA_NO_RFL_HI 298 299 /* 300 * Serial Port 301 */ 302 #define CONFIG_CONS_INDEX 2 303 #define CONFIG_SYS_NS16550_SERIAL 304 #define CONFIG_SYS_NS16550_REG_SIZE 1 305 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 306 307 #define CONFIG_SYS_BAUDRATE_TABLE \ 308 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 309 310 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 311 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 312 313 /* Pass open firmware flat tree */ 314 315 /* I2C */ 316 #define CONFIG_SYS_I2C 317 #define CONFIG_SYS_I2C_FSL 318 #define CONFIG_SYS_FSL_I2C_SPEED 400000 319 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 320 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 321 322 #define CONFIG_PCA953X /* NXP PCA9554 */ 323 #define CONFIG_CMD_PCA953X 324 #define CONFIG_CMD_PCA953X_INFO 325 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x24, 16}, {0x25, 16}, {0x26, 16}, \ 326 {0x3c, 8}, {0x3d, 8}, {0x3e, 8} } 327 328 #define CONFIG_PCA9698 /* NXP PCA9698 */ 329 330 #define CONFIG_SYS_I2C_IHS 331 #define CONFIG_SYS_I2C_IHS_CH0 332 #define CONFIG_SYS_I2C_IHS_SPEED_0 50000 333 #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F 334 #define CONFIG_SYS_I2C_IHS_CH1 335 #define CONFIG_SYS_I2C_IHS_SPEED_1 50000 336 #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F 337 #define CONFIG_SYS_I2C_IHS_CH2 338 #define CONFIG_SYS_I2C_IHS_SPEED_2 50000 339 #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F 340 #define CONFIG_SYS_I2C_IHS_CH3 341 #define CONFIG_SYS_I2C_IHS_SPEED_3 50000 342 #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F 343 344 /* 345 * Software (bit-bang) I2C driver configuration 346 */ 347 #define CONFIG_SYS_I2C_SOFT 348 #define CONFIG_SOFT_I2C_READ_REPEATED_START 349 #define CONFIG_SYS_I2C_SOFT_SPEED 50000 350 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F 351 #define I2C_SOFT_DECLARATIONS2 352 #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 353 #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F 354 #define I2C_SOFT_DECLARATIONS3 355 #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000 356 #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F 357 #define I2C_SOFT_DECLARATIONS4 358 #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 359 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F 360 #ifdef CONFIG_STRIDER_CON 361 #define I2C_SOFT_DECLARATIONS5 362 #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000 363 #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F 364 #define I2C_SOFT_DECLARATIONS6 365 #define CONFIG_SYS_I2C_SOFT_SPEED_6 50000 366 #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F 367 #define I2C_SOFT_DECLARATIONS7 368 #define CONFIG_SYS_I2C_SOFT_SPEED_7 50000 369 #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F 370 #define I2C_SOFT_DECLARATIONS8 371 #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000 372 #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F 373 #endif 374 375 #ifdef CONFIG_STRIDER_CON 376 #define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8} 377 #define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8} 378 #define CONFIG_SYS_ADV7611_I2C {5, 6, 7, 8} 379 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 380 #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \ 381 {12, 0x4c} } 382 #else 383 #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4} 384 #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4} 385 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 386 #define CONFIG_STRIDER_FANS { {2, 0x18}, {3, 0x18}, \ 387 {4, 0x18} } 388 #endif 389 390 #ifndef __ASSEMBLY__ 391 void fpga_gpio_set(unsigned int bus, int pin); 392 void fpga_gpio_clear(unsigned int bus, int pin); 393 int fpga_gpio_get(unsigned int bus, int pin); 394 #endif 395 396 #ifdef CONFIG_STRIDER_CON 397 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040) 398 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020) 399 #define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \ 400 (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR) 401 #else 402 #define I2C_SDA_GPIO 0x0040 403 #define I2C_SCL_GPIO 0x0020 404 #define I2C_FPGA_IDX I2C_ADAP_HWNR 405 #endif 406 #define I2C_ACTIVE { } 407 #define I2C_TRISTATE { } 408 #define I2C_READ \ 409 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0) 410 #define I2C_SDA(bit) \ 411 do { \ 412 if (bit) \ 413 fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \ 414 else \ 415 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \ 416 } while (0) 417 #define I2C_SCL(bit) \ 418 do { \ 419 if (bit) \ 420 fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \ 421 else \ 422 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \ 423 } while (0) 424 #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ 425 426 /* 427 * Software (bit-bang) MII driver configuration 428 */ 429 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 430 #define CONFIG_BITBANGMII_MULTI 431 432 /* 433 * OSD Setup 434 */ 435 #define CONFIG_SYS_OSD_SCREENS 1 436 #define CONFIG_SYS_DP501_DIFFERENTIAL 437 #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ 438 439 /* 440 * General PCI 441 * Addresses are mapped 1-1. 442 */ 443 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 444 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 445 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 446 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 447 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 448 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 449 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 450 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 451 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 452 453 /* enable PCIE clock */ 454 #define CONFIG_SYS_SCCR_PCIEXP1CM 1 455 456 #define CONFIG_PCI 457 #define CONFIG_PCI_INDIRECT_BRIDGE 458 #define CONFIG_PCIE 459 460 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 461 462 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 463 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 464 465 /* 466 * TSEC 467 */ 468 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 469 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 470 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 471 472 /* 473 * TSEC ethernet configuration 474 */ 475 #define CONFIG_MII 1 /* MII PHY management */ 476 #define CONFIG_TSEC1 477 #define CONFIG_TSEC1_NAME "eTSEC0" 478 #define TSEC1_PHY_ADDR 1 479 #define TSEC1_PHYIDX 0 480 #define TSEC1_FLAGS 0 481 482 /* Options are: eTSEC[0-1] */ 483 #define CONFIG_ETHPRIME "eTSEC0" 484 485 /* 486 * Environment 487 */ 488 #if 1 489 #define CONFIG_ENV_IS_IN_FLASH 1 490 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 491 CONFIG_SYS_MONITOR_LEN) 492 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 493 #define CONFIG_ENV_SIZE 0x2000 494 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 495 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 496 #else 497 #define CONFIG_ENV_IS_NOWHERE 498 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 499 #endif 500 501 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 502 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 503 504 /* 505 * Command line configuration. 506 */ 507 #define CONFIG_CMD_PCI 508 509 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 510 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 511 512 /* 513 * Miscellaneous configurable options 514 */ 515 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 516 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 517 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 518 519 #undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ 520 521 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 522 523 #define CONFIG_SYS_CONSOLE_INFO_QUIET 524 525 /* Print Buffer Size */ 526 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 527 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 528 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 529 530 /* 531 * For booting Linux, the board info and command line data 532 * have to be in the first 256 MB of memory, since this is 533 * the maximum mapped by the Linux kernel during initialization. 534 */ 535 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 536 537 /* 538 * Core HID Setup 539 */ 540 #define CONFIG_SYS_HID0_INIT 0x000000000 541 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 542 HID0_ENABLE_INSTRUCTION_CACHE | \ 543 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 544 #define CONFIG_SYS_HID2 HID2_HBE 545 546 /* 547 * MMU Setup 548 */ 549 550 /* DDR: cache cacheable */ 551 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 552 BATL_MEMCOHERENCE) 553 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ 554 BATU_VS | BATU_VP) 555 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 556 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 557 558 /* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */ 559 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 560 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 561 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ 562 BATU_VP) 563 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 564 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 565 566 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 567 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 568 BATL_MEMCOHERENCE) 569 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ 570 BATU_VS | BATU_VP) 571 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 572 BATL_CACHEINHIBIT | \ 573 BATL_GUARDEDSTORAGE) 574 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 575 576 /* Stack in dcache: cacheable, no memory coherence */ 577 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 578 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 579 BATU_VS | BATU_VP) 580 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 581 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 582 583 /* 584 * Environment Configuration 585 */ 586 587 #define CONFIG_ENV_OVERWRITE 588 589 #if defined(CONFIG_TSEC_ENET) 590 #define CONFIG_HAS_ETH0 591 #endif 592 593 #define CONFIG_BAUDRATE 115200 594 595 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 596 597 #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ 598 599 #define CONFIG_HOSTNAME hrcon 600 #define CONFIG_ROOTPATH "/opt/nfsroot" 601 #define CONFIG_BOOTFILE "uImage" 602 603 #define CONFIG_PREBOOT /* enable preboot variable */ 604 605 #define CONFIG_EXTRA_ENV_SETTINGS \ 606 "netdev=eth0\0" \ 607 "consoledev=ttyS1\0" \ 608 "u-boot=u-boot.bin\0" \ 609 "kernel_addr=1000000\0" \ 610 "fdt_addr=C00000\0" \ 611 "fdtfile=hrcon.dtb\0" \ 612 "load=tftp ${loadaddr} ${u-boot}\0" \ 613 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 614 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ 615 " +${filesize};cp.b ${fileaddr} " \ 616 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 617 "upd=run load update\0" \ 618 619 #define CONFIG_NFSBOOTCOMMAND \ 620 "setenv bootargs root=/dev/nfs rw " \ 621 "nfsroot=$serverip:$rootpath " \ 622 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 623 "console=$consoledev,$baudrate $othbootargs;" \ 624 "tftp ${kernel_addr} $bootfile;" \ 625 "tftp ${fdt_addr} $fdtfile;" \ 626 "bootm ${kernel_addr} - ${fdt_addr}" 627 628 #define CONFIG_MMCBOOTCOMMAND \ 629 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ 630 "console=$consoledev,$baudrate $othbootargs;" \ 631 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \ 632 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \ 633 "bootm ${kernel_addr} - ${fdt_addr}" 634 635 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND 636 637 #endif /* __CONFIG_H */ 638