1 /* 2 * (C) Copyright 2014 3 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc 4 * 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 /* E300 family */ 16 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 17 #define CONFIG_MPC830x 1 /* MPC830x family */ 18 #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ 19 #define CONFIG_STRIDER 1 /* STRIDER board specific */ 20 21 #define CONFIG_BOARD_EARLY_INIT_R 22 #define CONFIG_LAST_STAGE_INIT 23 24 #define CONFIG_FSL_ESDHC 25 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 26 27 #define CONFIG_SYS_ALT_MEMTEST 28 29 /* 30 * System Clock Setup 31 */ 32 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 33 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 34 35 /* 36 * Hardware Reset Configuration Word 37 * if CLKIN is 66.66MHz, then 38 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz 39 * We choose the A type silicon as default, so the core is 400Mhz. 40 */ 41 #define CONFIG_SYS_HRCW_LOW (\ 42 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 43 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 44 HRCWL_SVCOD_DIV_2 |\ 45 HRCWL_CSB_TO_CLKIN_4X1 |\ 46 HRCWL_CORE_TO_CSB_3X1) 47 /* 48 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits 49 * in 8308's HRCWH according to the manual, but original Freescale's 50 * code has them and I've expirienced some problems using the board 51 * with BDI3000 attached when I've tried to set these bits to zero 52 * (UART doesn't work after the 'reset run' command). 53 */ 54 #define CONFIG_SYS_HRCW_HIGH (\ 55 HRCWH_PCI_HOST |\ 56 HRCWH_PCI1_ARBITER_ENABLE |\ 57 HRCWH_CORE_ENABLE |\ 58 HRCWH_FROM_0XFFF00100 |\ 59 HRCWH_BOOTSEQ_DISABLE |\ 60 HRCWH_SW_WATCHDOG_DISABLE |\ 61 HRCWH_ROM_LOC_LOCAL_16BIT |\ 62 HRCWH_RL_EXT_LEGACY |\ 63 HRCWH_TSEC1M_IN_MII |\ 64 HRCWH_TSEC2M_IN_RGMII |\ 65 HRCWH_BIG_ENDIAN) 66 67 /* 68 * System IO Config 69 */ 70 #define CONFIG_SYS_SICRH (\ 71 SICRH_ESDHC_A_SD |\ 72 SICRH_ESDHC_B_SD |\ 73 SICRH_ESDHC_C_SD |\ 74 SICRH_GPIO_A_GPIO |\ 75 SICRH_GPIO_B_GPIO |\ 76 SICRH_IEEE1588_A_GPIO |\ 77 SICRH_USB |\ 78 SICRH_GTM_GPIO |\ 79 SICRH_IEEE1588_B_GPIO |\ 80 SICRH_ETSEC2_GPIO |\ 81 SICRH_GPIOSEL_1 |\ 82 SICRH_TMROBI_V3P3 |\ 83 SICRH_TSOBI1_V2P5 |\ 84 SICRH_TSOBI2_V2P5) /* 0x0037f103 */ 85 #define CONFIG_SYS_SICRL (\ 86 SICRL_SPI_PF0 |\ 87 SICRL_UART_PF0 |\ 88 SICRL_IRQ_PF0 |\ 89 SICRL_I2C2_PF0 |\ 90 SICRL_ETSEC1_TX_CLK) /* 0x00000000 */ 91 92 /* 93 * IMMR new address 94 */ 95 #define CONFIG_SYS_IMMR 0xE0000000 96 97 /* 98 * SERDES 99 */ 100 #define CONFIG_FSL_SERDES 101 #define CONFIG_FSL_SERDES1 0xe3000 102 103 /* 104 * Arbiter Setup 105 */ 106 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 107 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 108 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 109 110 /* 111 * DDR Setup 112 */ 113 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 114 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 115 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 116 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 117 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 118 | DDRCDR_PZ_LOZ \ 119 | DDRCDR_NZ_LOZ \ 120 | DDRCDR_ODT \ 121 | DDRCDR_Q_DRN) 122 /* 0x7b880001 */ 123 /* 124 * Manually set up DDR parameters 125 * consist of one chip NT5TU64M16HG from NANYA 126 */ 127 128 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 129 130 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 131 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 132 | CSCONFIG_ODT_RD_NEVER \ 133 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 134 | CSCONFIG_BANK_BIT_3 \ 135 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 136 /* 0x80010102 */ 137 #define CONFIG_SYS_DDR_TIMING_3 0 138 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 139 | (0 << TIMING_CFG0_WRT_SHIFT) \ 140 | (0 << TIMING_CFG0_RRT_SHIFT) \ 141 | (0 << TIMING_CFG0_WWT_SHIFT) \ 142 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 143 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 144 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 145 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 146 /* 0x00260802 */ 147 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 148 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 149 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 150 | (7 << TIMING_CFG1_CASLAT_SHIFT) \ 151 | (9 << TIMING_CFG1_REFREC_SHIFT) \ 152 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 153 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 154 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 155 /* 0x26279222 */ 156 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ 157 | (4 << TIMING_CFG2_CPO_SHIFT) \ 158 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 159 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 160 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 161 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 162 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 163 /* 0x021848c5 */ 164 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \ 165 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 166 /* 0x08240100 */ 167 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 168 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 169 | SDRAM_CFG_DBW_16) 170 /* 0x43100000 */ 171 172 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 173 #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ 174 | (0x0242 << SDRAM_MODE_SD_SHIFT)) 175 /* ODT 150ohm CL=4, AL=0 on SDRAM */ 176 #define CONFIG_SYS_DDR_MODE2 0x00000000 177 178 /* 179 * Memory test 180 */ 181 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ 182 #define CONFIG_SYS_MEMTEST_END 0x07f00000 183 184 /* 185 * The reserved memory 186 */ 187 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 188 189 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 190 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 191 192 /* 193 * Initial RAM Base Address Setup 194 */ 195 #define CONFIG_SYS_INIT_RAM_LOCK 1 196 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 197 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 198 #define CONFIG_SYS_GBL_DATA_OFFSET \ 199 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 200 201 /* 202 * Local Bus Configuration & Clock Setup 203 */ 204 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 205 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 206 #define CONFIG_SYS_LBC_LBCR 0x00040000 207 208 /* 209 * FLASH on the Local Bus 210 */ 211 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 212 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 213 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 214 #define CONFIG_FLASH_CFI_LEGACY 215 #define CONFIG_SYS_FLASH_LEGACY_512Kx16 216 217 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 218 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ 219 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 220 221 /* Window base at flash base */ 222 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 223 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 224 225 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 226 | BR_PS_16 /* 16 bit port */ \ 227 | BR_MS_GPCM /* MSEL = GPCM */ \ 228 | BR_V) /* valid */ 229 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 230 | OR_UPM_XAM \ 231 | OR_GPCM_CSNT \ 232 | OR_GPCM_ACS_DIV2 \ 233 | OR_GPCM_XACS \ 234 | OR_GPCM_SCY_15 \ 235 | OR_GPCM_TRLX_SET \ 236 | OR_GPCM_EHTR_SET) 237 238 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 239 #define CONFIG_SYS_MAX_FLASH_SECT 135 240 241 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 242 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 243 244 /* 245 * FPGA 246 */ 247 #define CONFIG_SYS_FPGA0_BASE 0xE0600000 248 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ 249 250 /* Window base at FPGA base */ 251 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE 252 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB) 253 254 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \ 255 | BR_PS_16 /* 16 bit port */ \ 256 | BR_MS_GPCM /* MSEL = GPCM */ \ 257 | BR_V) /* valid */ 258 259 #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \ 260 | OR_UPM_XAM \ 261 | OR_GPCM_CSNT \ 262 | OR_GPCM_SCY_5 \ 263 | OR_GPCM_TRLX_CLEAR \ 264 | OR_GPCM_EHTR_CLEAR) 265 266 #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE 267 #define CONFIG_SYS_FPGA_DONE(k) 0x0010 268 269 #define CONFIG_SYS_FPGA_COUNT 1 270 271 #define CONFIG_SYS_MCLINK_MAX 3 272 273 #define CONFIG_SYS_FPGA_PTR \ 274 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL } 275 276 #define CONFIG_SYS_FPGA_NO_RFL_HI 277 278 /* 279 * Serial Port 280 */ 281 #define CONFIG_CONS_INDEX 2 282 #define CONFIG_SYS_NS16550_SERIAL 283 #define CONFIG_SYS_NS16550_REG_SIZE 1 284 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 285 286 #define CONFIG_SYS_BAUDRATE_TABLE \ 287 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 288 289 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 290 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 291 292 /* Pass open firmware flat tree */ 293 294 /* I2C */ 295 #define CONFIG_SYS_I2C 296 #define CONFIG_SYS_I2C_FSL 297 #define CONFIG_SYS_FSL_I2C_SPEED 400000 298 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 299 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 300 301 #define CONFIG_PCA953X /* NXP PCA9554 */ 302 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x24, 16}, {0x25, 16}, {0x26, 16}, \ 303 {0x3c, 8}, {0x3d, 8}, {0x3e, 8} } 304 305 #define CONFIG_PCA9698 /* NXP PCA9698 */ 306 307 #define CONFIG_SYS_I2C_IHS 308 #define CONFIG_SYS_I2C_IHS_CH0 309 #define CONFIG_SYS_I2C_IHS_SPEED_0 50000 310 #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F 311 #define CONFIG_SYS_I2C_IHS_CH1 312 #define CONFIG_SYS_I2C_IHS_SPEED_1 50000 313 #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F 314 #define CONFIG_SYS_I2C_IHS_CH2 315 #define CONFIG_SYS_I2C_IHS_SPEED_2 50000 316 #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F 317 #define CONFIG_SYS_I2C_IHS_CH3 318 #define CONFIG_SYS_I2C_IHS_SPEED_3 50000 319 #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F 320 321 #ifdef CONFIG_STRIDER_CON_DP 322 #define CONFIG_SYS_I2C_IHS_DUAL 323 #define CONFIG_SYS_I2C_IHS_CH0_1 324 #define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000 325 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F 326 #define CONFIG_SYS_I2C_IHS_CH1_1 327 #define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000 328 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F 329 #define CONFIG_SYS_I2C_IHS_CH2_1 330 #define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000 331 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F 332 #define CONFIG_SYS_I2C_IHS_CH3_1 333 #define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000 334 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F 335 #endif 336 337 /* 338 * Software (bit-bang) I2C driver configuration 339 */ 340 #define CONFIG_SYS_I2C_SOFT 341 #define CONFIG_SOFT_I2C_READ_REPEATED_START 342 #define CONFIG_SYS_I2C_SOFT_SPEED 50000 343 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F 344 #define I2C_SOFT_DECLARATIONS2 345 #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 346 #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F 347 #define I2C_SOFT_DECLARATIONS3 348 #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000 349 #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F 350 #define I2C_SOFT_DECLARATIONS4 351 #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 352 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F 353 #if defined(CONFIG_STRIDER_CON) || defined(CONFIG_STRIDER_CON_DP) 354 #define I2C_SOFT_DECLARATIONS5 355 #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000 356 #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F 357 #define I2C_SOFT_DECLARATIONS6 358 #define CONFIG_SYS_I2C_SOFT_SPEED_6 50000 359 #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F 360 #define I2C_SOFT_DECLARATIONS7 361 #define CONFIG_SYS_I2C_SOFT_SPEED_7 50000 362 #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F 363 #define I2C_SOFT_DECLARATIONS8 364 #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000 365 #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F 366 #endif 367 #ifdef CONFIG_STRIDER_CON_DP 368 #define I2C_SOFT_DECLARATIONS9 369 #define CONFIG_SYS_I2C_SOFT_SPEED_9 50000 370 #define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F 371 #define I2C_SOFT_DECLARATIONS10 372 #define CONFIG_SYS_I2C_SOFT_SPEED_10 50000 373 #define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F 374 #define I2C_SOFT_DECLARATIONS11 375 #define CONFIG_SYS_I2C_SOFT_SPEED_11 50000 376 #define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F 377 #define I2C_SOFT_DECLARATIONS12 378 #define CONFIG_SYS_I2C_SOFT_SPEED_12 50000 379 #define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F 380 #endif 381 382 #ifdef CONFIG_STRIDER_CON 383 #define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8} 384 #define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8} 385 #define CONFIG_SYS_ADV7611_I2C {5, 6, 7, 8} 386 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 387 #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \ 388 {12, 0x4c} } 389 #elif defined(CONFIG_STRIDER_CON_DP) 390 #define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20} 391 #define CONFIG_SYS_CH7301_I2C {1, 3, 5, 7} 392 #define CONFIG_SYS_ADV7611_I2C {1, 3, 5, 7} 393 #define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8} 394 #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \ 395 {12, 0x4c} } 396 #elif defined(CONFIG_STRIDER_CPU_DP) 397 #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4} 398 #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4} 399 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 400 #define CONFIG_STRIDER_FANS { {6, 0x4c}, {7, 0x4c}, \ 401 {8, 0x4c} } 402 #else 403 #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4} 404 #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4} 405 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 406 #define CONFIG_STRIDER_FANS { {2, 0x18}, {3, 0x18}, \ 407 {4, 0x18} } 408 #endif 409 410 #ifndef __ASSEMBLY__ 411 void fpga_gpio_set(unsigned int bus, int pin); 412 void fpga_gpio_clear(unsigned int bus, int pin); 413 int fpga_gpio_get(unsigned int bus, int pin); 414 void fpga_control_set(unsigned int bus, int pin); 415 void fpga_control_clear(unsigned int bus, int pin); 416 #endif 417 418 #ifdef CONFIG_STRIDER_CON 419 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040) 420 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020) 421 #define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \ 422 (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR) 423 #elif defined(CONFIG_STRIDER_CON_DP) 424 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200) 425 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100) 426 #define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4) 427 #else 428 #define I2C_SDA_GPIO 0x0040 429 #define I2C_SCL_GPIO 0x0020 430 #define I2C_FPGA_IDX I2C_ADAP_HWNR 431 #endif 432 433 #ifdef CONFIG_STRIDER_CON_DP 434 #define I2C_ACTIVE \ 435 do { \ 436 if (I2C_ADAP_HWNR > 7) \ 437 fpga_control_set(I2C_FPGA_IDX, 0x0004); \ 438 else \ 439 fpga_control_clear(I2C_FPGA_IDX, 0x0004); \ 440 } while (0) 441 #else 442 #define I2C_ACTIVE { } 443 #endif 444 445 #define I2C_TRISTATE { } 446 #define I2C_READ \ 447 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0) 448 #define I2C_SDA(bit) \ 449 do { \ 450 if (bit) \ 451 fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \ 452 else \ 453 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \ 454 } while (0) 455 #define I2C_SCL(bit) \ 456 do { \ 457 if (bit) \ 458 fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \ 459 else \ 460 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \ 461 } while (0) 462 #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ 463 464 /* 465 * Software (bit-bang) MII driver configuration 466 */ 467 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 468 #define CONFIG_BITBANGMII_MULTI 469 470 /* 471 * OSD Setup 472 */ 473 #define CONFIG_SYS_OSD_SCREENS 1 474 #define CONFIG_SYS_DP501_DIFFERENTIAL 475 #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ 476 477 #ifdef CONFIG_STRIDER_CON_DP 478 #define CONFIG_SYS_OSD_DH 479 #endif 480 481 /* 482 * General PCI 483 * Addresses are mapped 1-1. 484 */ 485 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 486 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 487 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 488 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 489 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 490 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 491 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 492 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 493 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 494 495 /* enable PCIE clock */ 496 #define CONFIG_SYS_SCCR_PCIEXP1CM 1 497 498 #define CONFIG_PCI_INDIRECT_BRIDGE 499 #define CONFIG_PCIE 500 501 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 502 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 503 504 /* 505 * TSEC 506 */ 507 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 508 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 509 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 510 511 /* 512 * TSEC ethernet configuration 513 */ 514 #define CONFIG_MII 1 /* MII PHY management */ 515 #define CONFIG_TSEC1 516 #define CONFIG_TSEC1_NAME "eTSEC0" 517 #define TSEC1_PHY_ADDR 1 518 #define TSEC1_PHYIDX 0 519 #define TSEC1_FLAGS 0 520 521 /* Options are: eTSEC[0-1] */ 522 #define CONFIG_ETHPRIME "eTSEC0" 523 524 /* 525 * Environment 526 */ 527 #if 1 528 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 529 CONFIG_SYS_MONITOR_LEN) 530 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 531 #define CONFIG_ENV_SIZE 0x2000 532 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 533 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 534 #else 535 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 536 #endif 537 538 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 539 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 540 541 /* 542 * Command line configuration. 543 */ 544 545 /* 546 * Miscellaneous configurable options 547 */ 548 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 549 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 550 551 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 552 553 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 554 555 /* 556 * For booting Linux, the board info and command line data 557 * have to be in the first 256 MB of memory, since this is 558 * the maximum mapped by the Linux kernel during initialization. 559 */ 560 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 561 562 /* 563 * Core HID Setup 564 */ 565 #define CONFIG_SYS_HID0_INIT 0x000000000 566 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 567 HID0_ENABLE_INSTRUCTION_CACHE | \ 568 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 569 #define CONFIG_SYS_HID2 HID2_HBE 570 571 /* 572 * MMU Setup 573 */ 574 575 /* DDR: cache cacheable */ 576 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 577 BATL_MEMCOHERENCE) 578 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ 579 BATU_VS | BATU_VP) 580 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 581 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 582 583 /* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */ 584 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 585 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 586 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ 587 BATU_VP) 588 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 589 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 590 591 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 592 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 593 BATL_MEMCOHERENCE) 594 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ 595 BATU_VS | BATU_VP) 596 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 597 BATL_CACHEINHIBIT | \ 598 BATL_GUARDEDSTORAGE) 599 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 600 601 /* Stack in dcache: cacheable, no memory coherence */ 602 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 603 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 604 BATU_VS | BATU_VP) 605 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 606 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 607 608 /* 609 * Environment Configuration 610 */ 611 612 #define CONFIG_ENV_OVERWRITE 613 614 #if defined(CONFIG_TSEC_ENET) 615 #define CONFIG_HAS_ETH0 616 #endif 617 618 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 619 620 621 #define CONFIG_HOSTNAME hrcon 622 #define CONFIG_ROOTPATH "/opt/nfsroot" 623 #define CONFIG_BOOTFILE "uImage" 624 625 #define CONFIG_PREBOOT /* enable preboot variable */ 626 627 #define CONFIG_EXTRA_ENV_SETTINGS \ 628 "netdev=eth0\0" \ 629 "consoledev=ttyS1\0" \ 630 "u-boot=u-boot.bin\0" \ 631 "kernel_addr=1000000\0" \ 632 "fdt_addr=C00000\0" \ 633 "fdtfile=hrcon.dtb\0" \ 634 "load=tftp ${loadaddr} ${u-boot}\0" \ 635 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 636 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ 637 " +${filesize};cp.b ${fileaddr} " \ 638 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 639 "upd=run load update\0" \ 640 641 #define CONFIG_NFSBOOTCOMMAND \ 642 "setenv bootargs root=/dev/nfs rw " \ 643 "nfsroot=$serverip:$rootpath " \ 644 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 645 "console=$consoledev,$baudrate $othbootargs;" \ 646 "tftp ${kernel_addr} $bootfile;" \ 647 "tftp ${fdt_addr} $fdtfile;" \ 648 "bootm ${kernel_addr} - ${fdt_addr}" 649 650 #define CONFIG_MMCBOOTCOMMAND \ 651 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ 652 "console=$consoledev,$baudrate $othbootargs;" \ 653 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \ 654 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \ 655 "bootm ${kernel_addr} - ${fdt_addr}" 656 657 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND 658 659 #endif /* __CONFIG_H */ 660