1 /* 2 * (C) Copyright 2014 3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de 4 * 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 /* E300 family */ 16 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 17 #define CONFIG_MPC830x 1 /* MPC830x family */ 18 #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ 19 #define CONFIG_STRIDER 1 /* STRIDER board specific */ 20 21 #define CONFIG_SYS_TEXT_BASE 0xFE000000 22 23 #define CONFIG_BOARD_EARLY_INIT_R 24 #define CONFIG_LAST_STAGE_INIT 25 26 #define CONFIG_FSL_ESDHC 27 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 28 29 #define CONFIG_SYS_ALT_MEMTEST 30 31 /* 32 * System Clock Setup 33 */ 34 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 35 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 36 37 /* 38 * Hardware Reset Configuration Word 39 * if CLKIN is 66.66MHz, then 40 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz 41 * We choose the A type silicon as default, so the core is 400Mhz. 42 */ 43 #define CONFIG_SYS_HRCW_LOW (\ 44 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 45 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 46 HRCWL_SVCOD_DIV_2 |\ 47 HRCWL_CSB_TO_CLKIN_4X1 |\ 48 HRCWL_CORE_TO_CSB_3X1) 49 /* 50 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits 51 * in 8308's HRCWH according to the manual, but original Freescale's 52 * code has them and I've expirienced some problems using the board 53 * with BDI3000 attached when I've tried to set these bits to zero 54 * (UART doesn't work after the 'reset run' command). 55 */ 56 #define CONFIG_SYS_HRCW_HIGH (\ 57 HRCWH_PCI_HOST |\ 58 HRCWH_PCI1_ARBITER_ENABLE |\ 59 HRCWH_CORE_ENABLE |\ 60 HRCWH_FROM_0XFFF00100 |\ 61 HRCWH_BOOTSEQ_DISABLE |\ 62 HRCWH_SW_WATCHDOG_DISABLE |\ 63 HRCWH_ROM_LOC_LOCAL_16BIT |\ 64 HRCWH_RL_EXT_LEGACY |\ 65 HRCWH_TSEC1M_IN_MII |\ 66 HRCWH_TSEC2M_IN_RGMII |\ 67 HRCWH_BIG_ENDIAN) 68 69 /* 70 * System IO Config 71 */ 72 #define CONFIG_SYS_SICRH (\ 73 SICRH_ESDHC_A_SD |\ 74 SICRH_ESDHC_B_SD |\ 75 SICRH_ESDHC_C_SD |\ 76 SICRH_GPIO_A_GPIO |\ 77 SICRH_GPIO_B_GPIO |\ 78 SICRH_IEEE1588_A_GPIO |\ 79 SICRH_USB |\ 80 SICRH_GTM_GPIO |\ 81 SICRH_IEEE1588_B_GPIO |\ 82 SICRH_ETSEC2_GPIO |\ 83 SICRH_GPIOSEL_1 |\ 84 SICRH_TMROBI_V3P3 |\ 85 SICRH_TSOBI1_V2P5 |\ 86 SICRH_TSOBI2_V2P5) /* 0x0037f103 */ 87 #define CONFIG_SYS_SICRL (\ 88 SICRL_SPI_PF0 |\ 89 SICRL_UART_PF0 |\ 90 SICRL_IRQ_PF0 |\ 91 SICRL_I2C2_PF0 |\ 92 SICRL_ETSEC1_TX_CLK) /* 0x00000000 */ 93 94 /* 95 * IMMR new address 96 */ 97 #define CONFIG_SYS_IMMR 0xE0000000 98 99 /* 100 * SERDES 101 */ 102 #define CONFIG_FSL_SERDES 103 #define CONFIG_FSL_SERDES1 0xe3000 104 105 /* 106 * Arbiter Setup 107 */ 108 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 109 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 110 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 111 112 /* 113 * DDR Setup 114 */ 115 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 116 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 117 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 118 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 119 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 120 | DDRCDR_PZ_LOZ \ 121 | DDRCDR_NZ_LOZ \ 122 | DDRCDR_ODT \ 123 | DDRCDR_Q_DRN) 124 /* 0x7b880001 */ 125 /* 126 * Manually set up DDR parameters 127 * consist of one chip NT5TU64M16HG from NANYA 128 */ 129 130 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 131 132 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 133 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 134 | CSCONFIG_ODT_RD_NEVER \ 135 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 136 | CSCONFIG_BANK_BIT_3 \ 137 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 138 /* 0x80010102 */ 139 #define CONFIG_SYS_DDR_TIMING_3 0 140 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 141 | (0 << TIMING_CFG0_WRT_SHIFT) \ 142 | (0 << TIMING_CFG0_RRT_SHIFT) \ 143 | (0 << TIMING_CFG0_WWT_SHIFT) \ 144 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 145 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 146 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 147 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 148 /* 0x00260802 */ 149 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 150 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 151 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 152 | (7 << TIMING_CFG1_CASLAT_SHIFT) \ 153 | (9 << TIMING_CFG1_REFREC_SHIFT) \ 154 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 155 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 156 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 157 /* 0x26279222 */ 158 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ 159 | (4 << TIMING_CFG2_CPO_SHIFT) \ 160 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 161 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 162 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 163 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 164 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 165 /* 0x021848c5 */ 166 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \ 167 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 168 /* 0x08240100 */ 169 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 170 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 171 | SDRAM_CFG_DBW_16) 172 /* 0x43100000 */ 173 174 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 175 #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ 176 | (0x0242 << SDRAM_MODE_SD_SHIFT)) 177 /* ODT 150ohm CL=4, AL=0 on SDRAM */ 178 #define CONFIG_SYS_DDR_MODE2 0x00000000 179 180 /* 181 * Memory test 182 */ 183 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ 184 #define CONFIG_SYS_MEMTEST_END 0x07f00000 185 186 /* 187 * The reserved memory 188 */ 189 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 190 191 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 192 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 193 194 /* 195 * Initial RAM Base Address Setup 196 */ 197 #define CONFIG_SYS_INIT_RAM_LOCK 1 198 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 199 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 200 #define CONFIG_SYS_GBL_DATA_OFFSET \ 201 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 202 203 /* 204 * Local Bus Configuration & Clock Setup 205 */ 206 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 207 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 208 #define CONFIG_SYS_LBC_LBCR 0x00040000 209 210 /* 211 * FLASH on the Local Bus 212 */ 213 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 214 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 215 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 216 #define CONFIG_FLASH_CFI_LEGACY 217 #define CONFIG_SYS_FLASH_LEGACY_512Kx16 218 219 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 220 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ 221 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 222 223 /* Window base at flash base */ 224 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 225 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 226 227 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 228 | BR_PS_16 /* 16 bit port */ \ 229 | BR_MS_GPCM /* MSEL = GPCM */ \ 230 | BR_V) /* valid */ 231 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 232 | OR_UPM_XAM \ 233 | OR_GPCM_CSNT \ 234 | OR_GPCM_ACS_DIV2 \ 235 | OR_GPCM_XACS \ 236 | OR_GPCM_SCY_15 \ 237 | OR_GPCM_TRLX_SET \ 238 | OR_GPCM_EHTR_SET) 239 240 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 241 #define CONFIG_SYS_MAX_FLASH_SECT 135 242 243 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 244 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 245 246 /* 247 * FPGA 248 */ 249 #define CONFIG_SYS_FPGA0_BASE 0xE0600000 250 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ 251 252 /* Window base at FPGA base */ 253 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE 254 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB) 255 256 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \ 257 | BR_PS_16 /* 16 bit port */ \ 258 | BR_MS_GPCM /* MSEL = GPCM */ \ 259 | BR_V) /* valid */ 260 261 #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \ 262 | OR_UPM_XAM \ 263 | OR_GPCM_CSNT \ 264 | OR_GPCM_SCY_5 \ 265 | OR_GPCM_TRLX_CLEAR \ 266 | OR_GPCM_EHTR_CLEAR) 267 268 #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE 269 #define CONFIG_SYS_FPGA_DONE(k) 0x0010 270 271 #define CONFIG_SYS_FPGA_COUNT 1 272 273 #define CONFIG_SYS_MCLINK_MAX 3 274 275 #define CONFIG_SYS_FPGA_PTR \ 276 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL } 277 278 #define CONFIG_SYS_FPGA_NO_RFL_HI 279 280 /* 281 * Serial Port 282 */ 283 #define CONFIG_CONS_INDEX 2 284 #define CONFIG_SYS_NS16550_SERIAL 285 #define CONFIG_SYS_NS16550_REG_SIZE 1 286 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 287 288 #define CONFIG_SYS_BAUDRATE_TABLE \ 289 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 290 291 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 292 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 293 294 /* Pass open firmware flat tree */ 295 296 /* I2C */ 297 #define CONFIG_SYS_I2C 298 #define CONFIG_SYS_I2C_FSL 299 #define CONFIG_SYS_FSL_I2C_SPEED 400000 300 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 301 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 302 303 #define CONFIG_PCA953X /* NXP PCA9554 */ 304 #define CONFIG_CMD_PCA953X 305 #define CONFIG_CMD_PCA953X_INFO 306 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x24, 16}, {0x25, 16}, {0x26, 16}, \ 307 {0x3c, 8}, {0x3d, 8}, {0x3e, 8} } 308 309 #define CONFIG_PCA9698 /* NXP PCA9698 */ 310 311 #define CONFIG_SYS_I2C_IHS 312 #define CONFIG_SYS_I2C_IHS_CH0 313 #define CONFIG_SYS_I2C_IHS_SPEED_0 50000 314 #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F 315 #define CONFIG_SYS_I2C_IHS_CH1 316 #define CONFIG_SYS_I2C_IHS_SPEED_1 50000 317 #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F 318 #define CONFIG_SYS_I2C_IHS_CH2 319 #define CONFIG_SYS_I2C_IHS_SPEED_2 50000 320 #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F 321 #define CONFIG_SYS_I2C_IHS_CH3 322 #define CONFIG_SYS_I2C_IHS_SPEED_3 50000 323 #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F 324 325 #ifdef CONFIG_STRIDER_CON_DP 326 #define CONFIG_SYS_I2C_IHS_DUAL 327 #define CONFIG_SYS_I2C_IHS_CH0_1 328 #define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000 329 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F 330 #define CONFIG_SYS_I2C_IHS_CH1_1 331 #define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000 332 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F 333 #define CONFIG_SYS_I2C_IHS_CH2_1 334 #define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000 335 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F 336 #define CONFIG_SYS_I2C_IHS_CH3_1 337 #define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000 338 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F 339 #endif 340 341 /* 342 * Software (bit-bang) I2C driver configuration 343 */ 344 #define CONFIG_SYS_I2C_SOFT 345 #define CONFIG_SOFT_I2C_READ_REPEATED_START 346 #define CONFIG_SYS_I2C_SOFT_SPEED 50000 347 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F 348 #define I2C_SOFT_DECLARATIONS2 349 #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 350 #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F 351 #define I2C_SOFT_DECLARATIONS3 352 #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000 353 #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F 354 #define I2C_SOFT_DECLARATIONS4 355 #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 356 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F 357 #if defined(CONFIG_STRIDER_CON) || defined(CONFIG_STRIDER_CON_DP) 358 #define I2C_SOFT_DECLARATIONS5 359 #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000 360 #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F 361 #define I2C_SOFT_DECLARATIONS6 362 #define CONFIG_SYS_I2C_SOFT_SPEED_6 50000 363 #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F 364 #define I2C_SOFT_DECLARATIONS7 365 #define CONFIG_SYS_I2C_SOFT_SPEED_7 50000 366 #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F 367 #define I2C_SOFT_DECLARATIONS8 368 #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000 369 #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F 370 #endif 371 #ifdef CONFIG_STRIDER_CON_DP 372 #define I2C_SOFT_DECLARATIONS9 373 #define CONFIG_SYS_I2C_SOFT_SPEED_9 50000 374 #define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F 375 #define I2C_SOFT_DECLARATIONS10 376 #define CONFIG_SYS_I2C_SOFT_SPEED_10 50000 377 #define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F 378 #define I2C_SOFT_DECLARATIONS11 379 #define CONFIG_SYS_I2C_SOFT_SPEED_11 50000 380 #define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F 381 #define I2C_SOFT_DECLARATIONS12 382 #define CONFIG_SYS_I2C_SOFT_SPEED_12 50000 383 #define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F 384 #endif 385 386 #ifdef CONFIG_STRIDER_CON 387 #define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8} 388 #define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8} 389 #define CONFIG_SYS_ADV7611_I2C {5, 6, 7, 8} 390 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 391 #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \ 392 {12, 0x4c} } 393 #elif defined(CONFIG_STRIDER_CON_DP) 394 #define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20} 395 #define CONFIG_SYS_CH7301_I2C {1, 3, 5, 7} 396 #define CONFIG_SYS_ADV7611_I2C {1, 3, 5, 7} 397 #define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8} 398 #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \ 399 {12, 0x4c} } 400 #elif defined(CONFIG_STRIDER_CPU_DP) 401 #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4} 402 #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4} 403 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 404 #define CONFIG_STRIDER_FANS { {6, 0x4c}, {7, 0x4c}, \ 405 {8, 0x4c} } 406 #else 407 #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4} 408 #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4} 409 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 410 #define CONFIG_STRIDER_FANS { {2, 0x18}, {3, 0x18}, \ 411 {4, 0x18} } 412 #endif 413 414 #ifndef __ASSEMBLY__ 415 void fpga_gpio_set(unsigned int bus, int pin); 416 void fpga_gpio_clear(unsigned int bus, int pin); 417 int fpga_gpio_get(unsigned int bus, int pin); 418 void fpga_control_set(unsigned int bus, int pin); 419 void fpga_control_clear(unsigned int bus, int pin); 420 #endif 421 422 #ifdef CONFIG_STRIDER_CON 423 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040) 424 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020) 425 #define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \ 426 (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR) 427 #elif defined(CONFIG_STRIDER_CON_DP) 428 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200) 429 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100) 430 #define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4) 431 #else 432 #define I2C_SDA_GPIO 0x0040 433 #define I2C_SCL_GPIO 0x0020 434 #define I2C_FPGA_IDX I2C_ADAP_HWNR 435 #endif 436 437 #ifdef CONFIG_STRIDER_CON_DP 438 #define I2C_ACTIVE \ 439 do { \ 440 if (I2C_ADAP_HWNR > 7) \ 441 fpga_control_set(I2C_FPGA_IDX, 0x0004); \ 442 else \ 443 fpga_control_clear(I2C_FPGA_IDX, 0x0004); \ 444 } while (0) 445 #else 446 #define I2C_ACTIVE { } 447 #endif 448 449 #define I2C_TRISTATE { } 450 #define I2C_READ \ 451 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0) 452 #define I2C_SDA(bit) \ 453 do { \ 454 if (bit) \ 455 fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \ 456 else \ 457 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \ 458 } while (0) 459 #define I2C_SCL(bit) \ 460 do { \ 461 if (bit) \ 462 fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \ 463 else \ 464 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \ 465 } while (0) 466 #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ 467 468 /* 469 * Software (bit-bang) MII driver configuration 470 */ 471 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 472 #define CONFIG_BITBANGMII_MULTI 473 474 /* 475 * OSD Setup 476 */ 477 #define CONFIG_SYS_OSD_SCREENS 1 478 #define CONFIG_SYS_DP501_DIFFERENTIAL 479 #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ 480 481 #ifdef CONFIG_STRIDER_CON_DP 482 #define CONFIG_SYS_OSD_DH 483 #endif 484 485 /* 486 * General PCI 487 * Addresses are mapped 1-1. 488 */ 489 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 490 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 491 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 492 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 493 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 494 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 495 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 496 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 497 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 498 499 /* enable PCIE clock */ 500 #define CONFIG_SYS_SCCR_PCIEXP1CM 1 501 502 #define CONFIG_PCI_INDIRECT_BRIDGE 503 #define CONFIG_PCIE 504 505 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 506 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 507 508 /* 509 * TSEC 510 */ 511 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 512 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 513 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 514 515 /* 516 * TSEC ethernet configuration 517 */ 518 #define CONFIG_MII 1 /* MII PHY management */ 519 #define CONFIG_TSEC1 520 #define CONFIG_TSEC1_NAME "eTSEC0" 521 #define TSEC1_PHY_ADDR 1 522 #define TSEC1_PHYIDX 0 523 #define TSEC1_FLAGS 0 524 525 /* Options are: eTSEC[0-1] */ 526 #define CONFIG_ETHPRIME "eTSEC0" 527 528 /* 529 * Environment 530 */ 531 #if 1 532 #define CONFIG_ENV_IS_IN_FLASH 1 533 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 534 CONFIG_SYS_MONITOR_LEN) 535 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 536 #define CONFIG_ENV_SIZE 0x2000 537 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 538 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 539 #else 540 #define CONFIG_ENV_IS_NOWHERE 541 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 542 #endif 543 544 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 545 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 546 547 /* 548 * Command line configuration. 549 */ 550 #define CONFIG_CMD_PCI 551 552 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 553 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 554 555 /* 556 * Miscellaneous configurable options 557 */ 558 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 559 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 560 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 561 562 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 563 564 /* Print Buffer Size */ 565 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 566 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 567 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 568 569 /* 570 * For booting Linux, the board info and command line data 571 * have to be in the first 256 MB of memory, since this is 572 * the maximum mapped by the Linux kernel during initialization. 573 */ 574 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 575 576 /* 577 * Core HID Setup 578 */ 579 #define CONFIG_SYS_HID0_INIT 0x000000000 580 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 581 HID0_ENABLE_INSTRUCTION_CACHE | \ 582 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 583 #define CONFIG_SYS_HID2 HID2_HBE 584 585 /* 586 * MMU Setup 587 */ 588 589 /* DDR: cache cacheable */ 590 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 591 BATL_MEMCOHERENCE) 592 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ 593 BATU_VS | BATU_VP) 594 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 595 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 596 597 /* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */ 598 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 599 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 600 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ 601 BATU_VP) 602 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 603 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 604 605 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 606 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 607 BATL_MEMCOHERENCE) 608 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ 609 BATU_VS | BATU_VP) 610 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 611 BATL_CACHEINHIBIT | \ 612 BATL_GUARDEDSTORAGE) 613 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 614 615 /* Stack in dcache: cacheable, no memory coherence */ 616 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 617 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 618 BATU_VS | BATU_VP) 619 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 620 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 621 622 /* 623 * Environment Configuration 624 */ 625 626 #define CONFIG_ENV_OVERWRITE 627 628 #if defined(CONFIG_TSEC_ENET) 629 #define CONFIG_HAS_ETH0 630 #endif 631 632 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 633 634 635 #define CONFIG_HOSTNAME hrcon 636 #define CONFIG_ROOTPATH "/opt/nfsroot" 637 #define CONFIG_BOOTFILE "uImage" 638 639 #define CONFIG_PREBOOT /* enable preboot variable */ 640 641 #define CONFIG_EXTRA_ENV_SETTINGS \ 642 "netdev=eth0\0" \ 643 "consoledev=ttyS1\0" \ 644 "u-boot=u-boot.bin\0" \ 645 "kernel_addr=1000000\0" \ 646 "fdt_addr=C00000\0" \ 647 "fdtfile=hrcon.dtb\0" \ 648 "load=tftp ${loadaddr} ${u-boot}\0" \ 649 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 650 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ 651 " +${filesize};cp.b ${fileaddr} " \ 652 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 653 "upd=run load update\0" \ 654 655 #define CONFIG_NFSBOOTCOMMAND \ 656 "setenv bootargs root=/dev/nfs rw " \ 657 "nfsroot=$serverip:$rootpath " \ 658 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 659 "console=$consoledev,$baudrate $othbootargs;" \ 660 "tftp ${kernel_addr} $bootfile;" \ 661 "tftp ${fdt_addr} $fdtfile;" \ 662 "bootm ${kernel_addr} - ${fdt_addr}" 663 664 #define CONFIG_MMCBOOTCOMMAND \ 665 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ 666 "console=$consoledev,$baudrate $othbootargs;" \ 667 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \ 668 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \ 669 "bootm ${kernel_addr} - ${fdt_addr}" 670 671 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND 672 673 #endif /* __CONFIG_H */ 674