1 /* 2 * (C) Copyright 2014 3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de 4 * 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 /* E300 family */ 16 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 17 #define CONFIG_MPC830x 1 /* MPC830x family */ 18 #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ 19 #define CONFIG_STRIDER 1 /* STRIDER board specific */ 20 21 #define CONFIG_SYS_TEXT_BASE 0xFE000000 22 23 #define CONFIG_BOARD_EARLY_INIT_R 24 #define CONFIG_LAST_STAGE_INIT 25 26 #define CONFIG_FSL_ESDHC 27 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 28 29 #define CONFIG_SYS_ALT_MEMTEST 30 31 #define CONFIG_CMD_FPGAD 32 #define CONFIG_CMD_IOLOOP 33 34 /* 35 * System Clock Setup 36 */ 37 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 38 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 39 40 /* 41 * Hardware Reset Configuration Word 42 * if CLKIN is 66.66MHz, then 43 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz 44 * We choose the A type silicon as default, so the core is 400Mhz. 45 */ 46 #define CONFIG_SYS_HRCW_LOW (\ 47 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 48 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 49 HRCWL_SVCOD_DIV_2 |\ 50 HRCWL_CSB_TO_CLKIN_4X1 |\ 51 HRCWL_CORE_TO_CSB_3X1) 52 /* 53 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits 54 * in 8308's HRCWH according to the manual, but original Freescale's 55 * code has them and I've expirienced some problems using the board 56 * with BDI3000 attached when I've tried to set these bits to zero 57 * (UART doesn't work after the 'reset run' command). 58 */ 59 #define CONFIG_SYS_HRCW_HIGH (\ 60 HRCWH_PCI_HOST |\ 61 HRCWH_PCI1_ARBITER_ENABLE |\ 62 HRCWH_CORE_ENABLE |\ 63 HRCWH_FROM_0XFFF00100 |\ 64 HRCWH_BOOTSEQ_DISABLE |\ 65 HRCWH_SW_WATCHDOG_DISABLE |\ 66 HRCWH_ROM_LOC_LOCAL_16BIT |\ 67 HRCWH_RL_EXT_LEGACY |\ 68 HRCWH_TSEC1M_IN_MII |\ 69 HRCWH_TSEC2M_IN_RGMII |\ 70 HRCWH_BIG_ENDIAN) 71 72 /* 73 * System IO Config 74 */ 75 #define CONFIG_SYS_SICRH (\ 76 SICRH_ESDHC_A_SD |\ 77 SICRH_ESDHC_B_SD |\ 78 SICRH_ESDHC_C_SD |\ 79 SICRH_GPIO_A_GPIO |\ 80 SICRH_GPIO_B_GPIO |\ 81 SICRH_IEEE1588_A_GPIO |\ 82 SICRH_USB |\ 83 SICRH_GTM_GPIO |\ 84 SICRH_IEEE1588_B_GPIO |\ 85 SICRH_ETSEC2_GPIO |\ 86 SICRH_GPIOSEL_1 |\ 87 SICRH_TMROBI_V3P3 |\ 88 SICRH_TSOBI1_V2P5 |\ 89 SICRH_TSOBI2_V2P5) /* 0x0037f103 */ 90 #define CONFIG_SYS_SICRL (\ 91 SICRL_SPI_PF0 |\ 92 SICRL_UART_PF0 |\ 93 SICRL_IRQ_PF0 |\ 94 SICRL_I2C2_PF0 |\ 95 SICRL_ETSEC1_TX_CLK) /* 0x00000000 */ 96 97 /* 98 * IMMR new address 99 */ 100 #define CONFIG_SYS_IMMR 0xE0000000 101 102 /* 103 * SERDES 104 */ 105 #define CONFIG_FSL_SERDES 106 #define CONFIG_FSL_SERDES1 0xe3000 107 108 /* 109 * Arbiter Setup 110 */ 111 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 112 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 113 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 114 115 /* 116 * DDR Setup 117 */ 118 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 119 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 120 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 121 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 122 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 123 | DDRCDR_PZ_LOZ \ 124 | DDRCDR_NZ_LOZ \ 125 | DDRCDR_ODT \ 126 | DDRCDR_Q_DRN) 127 /* 0x7b880001 */ 128 /* 129 * Manually set up DDR parameters 130 * consist of one chip NT5TU64M16HG from NANYA 131 */ 132 133 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 134 135 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 136 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 137 | CSCONFIG_ODT_RD_NEVER \ 138 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 139 | CSCONFIG_BANK_BIT_3 \ 140 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 141 /* 0x80010102 */ 142 #define CONFIG_SYS_DDR_TIMING_3 0 143 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 144 | (0 << TIMING_CFG0_WRT_SHIFT) \ 145 | (0 << TIMING_CFG0_RRT_SHIFT) \ 146 | (0 << TIMING_CFG0_WWT_SHIFT) \ 147 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 148 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 149 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 150 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 151 /* 0x00260802 */ 152 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 153 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 154 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 155 | (7 << TIMING_CFG1_CASLAT_SHIFT) \ 156 | (9 << TIMING_CFG1_REFREC_SHIFT) \ 157 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 158 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 159 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 160 /* 0x26279222 */ 161 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ 162 | (4 << TIMING_CFG2_CPO_SHIFT) \ 163 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 164 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 165 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 166 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 167 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 168 /* 0x021848c5 */ 169 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \ 170 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 171 /* 0x08240100 */ 172 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 173 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 174 | SDRAM_CFG_DBW_16) 175 /* 0x43100000 */ 176 177 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 178 #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ 179 | (0x0242 << SDRAM_MODE_SD_SHIFT)) 180 /* ODT 150ohm CL=4, AL=0 on SDRAM */ 181 #define CONFIG_SYS_DDR_MODE2 0x00000000 182 183 /* 184 * Memory test 185 */ 186 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ 187 #define CONFIG_SYS_MEMTEST_END 0x07f00000 188 189 /* 190 * The reserved memory 191 */ 192 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 193 194 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 195 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 196 197 /* 198 * Initial RAM Base Address Setup 199 */ 200 #define CONFIG_SYS_INIT_RAM_LOCK 1 201 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 202 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 203 #define CONFIG_SYS_GBL_DATA_OFFSET \ 204 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 205 206 /* 207 * Local Bus Configuration & Clock Setup 208 */ 209 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 210 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 211 #define CONFIG_SYS_LBC_LBCR 0x00040000 212 213 /* 214 * FLASH on the Local Bus 215 */ 216 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 217 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 218 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 219 #define CONFIG_FLASH_CFI_LEGACY 220 #define CONFIG_SYS_FLASH_LEGACY_512Kx16 221 222 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 223 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ 224 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 225 226 /* Window base at flash base */ 227 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 228 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 229 230 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 231 | BR_PS_16 /* 16 bit port */ \ 232 | BR_MS_GPCM /* MSEL = GPCM */ \ 233 | BR_V) /* valid */ 234 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 235 | OR_UPM_XAM \ 236 | OR_GPCM_CSNT \ 237 | OR_GPCM_ACS_DIV2 \ 238 | OR_GPCM_XACS \ 239 | OR_GPCM_SCY_15 \ 240 | OR_GPCM_TRLX_SET \ 241 | OR_GPCM_EHTR_SET) 242 243 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 244 #define CONFIG_SYS_MAX_FLASH_SECT 135 245 246 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 247 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 248 249 /* 250 * FPGA 251 */ 252 #define CONFIG_SYS_FPGA0_BASE 0xE0600000 253 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ 254 255 /* Window base at FPGA base */ 256 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE 257 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB) 258 259 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \ 260 | BR_PS_16 /* 16 bit port */ \ 261 | BR_MS_GPCM /* MSEL = GPCM */ \ 262 | BR_V) /* valid */ 263 264 #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \ 265 | OR_UPM_XAM \ 266 | OR_GPCM_CSNT \ 267 | OR_GPCM_SCY_5 \ 268 | OR_GPCM_TRLX_CLEAR \ 269 | OR_GPCM_EHTR_CLEAR) 270 271 #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE 272 #define CONFIG_SYS_FPGA_DONE(k) 0x0010 273 274 #define CONFIG_SYS_FPGA_COUNT 1 275 276 #define CONFIG_SYS_MCLINK_MAX 3 277 278 #define CONFIG_SYS_FPGA_PTR \ 279 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL } 280 281 #define CONFIG_SYS_FPGA_NO_RFL_HI 282 283 /* 284 * Serial Port 285 */ 286 #define CONFIG_CONS_INDEX 2 287 #define CONFIG_SYS_NS16550_SERIAL 288 #define CONFIG_SYS_NS16550_REG_SIZE 1 289 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 290 291 #define CONFIG_SYS_BAUDRATE_TABLE \ 292 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 293 294 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 295 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 296 297 /* Pass open firmware flat tree */ 298 299 /* I2C */ 300 #define CONFIG_SYS_I2C 301 #define CONFIG_SYS_I2C_FSL 302 #define CONFIG_SYS_FSL_I2C_SPEED 400000 303 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 304 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 305 306 #define CONFIG_PCA953X /* NXP PCA9554 */ 307 #define CONFIG_CMD_PCA953X 308 #define CONFIG_CMD_PCA953X_INFO 309 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x24, 16}, {0x25, 16}, {0x26, 16}, \ 310 {0x3c, 8}, {0x3d, 8}, {0x3e, 8} } 311 312 #define CONFIG_PCA9698 /* NXP PCA9698 */ 313 314 #define CONFIG_SYS_I2C_IHS 315 #define CONFIG_SYS_I2C_IHS_CH0 316 #define CONFIG_SYS_I2C_IHS_SPEED_0 50000 317 #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F 318 #define CONFIG_SYS_I2C_IHS_CH1 319 #define CONFIG_SYS_I2C_IHS_SPEED_1 50000 320 #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F 321 #define CONFIG_SYS_I2C_IHS_CH2 322 #define CONFIG_SYS_I2C_IHS_SPEED_2 50000 323 #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F 324 #define CONFIG_SYS_I2C_IHS_CH3 325 #define CONFIG_SYS_I2C_IHS_SPEED_3 50000 326 #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F 327 328 #ifdef CONFIG_STRIDER_CON_DP 329 #define CONFIG_SYS_I2C_IHS_DUAL 330 #define CONFIG_SYS_I2C_IHS_CH0_1 331 #define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000 332 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F 333 #define CONFIG_SYS_I2C_IHS_CH1_1 334 #define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000 335 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F 336 #define CONFIG_SYS_I2C_IHS_CH2_1 337 #define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000 338 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F 339 #define CONFIG_SYS_I2C_IHS_CH3_1 340 #define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000 341 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F 342 #endif 343 344 /* 345 * Software (bit-bang) I2C driver configuration 346 */ 347 #define CONFIG_SYS_I2C_SOFT 348 #define CONFIG_SOFT_I2C_READ_REPEATED_START 349 #define CONFIG_SYS_I2C_SOFT_SPEED 50000 350 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F 351 #define I2C_SOFT_DECLARATIONS2 352 #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 353 #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F 354 #define I2C_SOFT_DECLARATIONS3 355 #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000 356 #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F 357 #define I2C_SOFT_DECLARATIONS4 358 #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 359 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F 360 #if defined(CONFIG_STRIDER_CON) || defined(CONFIG_STRIDER_CON_DP) 361 #define I2C_SOFT_DECLARATIONS5 362 #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000 363 #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F 364 #define I2C_SOFT_DECLARATIONS6 365 #define CONFIG_SYS_I2C_SOFT_SPEED_6 50000 366 #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F 367 #define I2C_SOFT_DECLARATIONS7 368 #define CONFIG_SYS_I2C_SOFT_SPEED_7 50000 369 #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F 370 #define I2C_SOFT_DECLARATIONS8 371 #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000 372 #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F 373 #endif 374 #ifdef CONFIG_STRIDER_CON_DP 375 #define I2C_SOFT_DECLARATIONS9 376 #define CONFIG_SYS_I2C_SOFT_SPEED_9 50000 377 #define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F 378 #define I2C_SOFT_DECLARATIONS10 379 #define CONFIG_SYS_I2C_SOFT_SPEED_10 50000 380 #define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F 381 #define I2C_SOFT_DECLARATIONS11 382 #define CONFIG_SYS_I2C_SOFT_SPEED_11 50000 383 #define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F 384 #define I2C_SOFT_DECLARATIONS12 385 #define CONFIG_SYS_I2C_SOFT_SPEED_12 50000 386 #define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F 387 #endif 388 389 #ifdef CONFIG_STRIDER_CON 390 #define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8} 391 #define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8} 392 #define CONFIG_SYS_ADV7611_I2C {5, 6, 7, 8} 393 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 394 #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \ 395 {12, 0x4c} } 396 #elif defined(CONFIG_STRIDER_CON_DP) 397 #define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20} 398 #define CONFIG_SYS_CH7301_I2C {1, 3, 5, 7} 399 #define CONFIG_SYS_ADV7611_I2C {1, 3, 5, 7} 400 #define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8} 401 #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \ 402 {12, 0x4c} } 403 #elif defined(CONFIG_STRIDER_CPU_DP) 404 #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4} 405 #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4} 406 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 407 #define CONFIG_STRIDER_FANS { {6, 0x4c}, {7, 0x4c}, \ 408 {8, 0x4c} } 409 #else 410 #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4} 411 #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4} 412 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 413 #define CONFIG_STRIDER_FANS { {2, 0x18}, {3, 0x18}, \ 414 {4, 0x18} } 415 #endif 416 417 #ifndef __ASSEMBLY__ 418 void fpga_gpio_set(unsigned int bus, int pin); 419 void fpga_gpio_clear(unsigned int bus, int pin); 420 int fpga_gpio_get(unsigned int bus, int pin); 421 void fpga_control_set(unsigned int bus, int pin); 422 void fpga_control_clear(unsigned int bus, int pin); 423 #endif 424 425 #ifdef CONFIG_STRIDER_CON 426 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040) 427 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020) 428 #define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \ 429 (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR) 430 #elif defined(CONFIG_STRIDER_CON_DP) 431 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200) 432 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100) 433 #define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4) 434 #else 435 #define I2C_SDA_GPIO 0x0040 436 #define I2C_SCL_GPIO 0x0020 437 #define I2C_FPGA_IDX I2C_ADAP_HWNR 438 #endif 439 440 #ifdef CONFIG_STRIDER_CON_DP 441 #define I2C_ACTIVE \ 442 do { \ 443 if (I2C_ADAP_HWNR > 7) \ 444 fpga_control_set(I2C_FPGA_IDX, 0x0004); \ 445 else \ 446 fpga_control_clear(I2C_FPGA_IDX, 0x0004); \ 447 } while (0) 448 #else 449 #define I2C_ACTIVE { } 450 #endif 451 452 #define I2C_TRISTATE { } 453 #define I2C_READ \ 454 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0) 455 #define I2C_SDA(bit) \ 456 do { \ 457 if (bit) \ 458 fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \ 459 else \ 460 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \ 461 } while (0) 462 #define I2C_SCL(bit) \ 463 do { \ 464 if (bit) \ 465 fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \ 466 else \ 467 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \ 468 } while (0) 469 #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ 470 471 /* 472 * Software (bit-bang) MII driver configuration 473 */ 474 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 475 #define CONFIG_BITBANGMII_MULTI 476 477 /* 478 * OSD Setup 479 */ 480 #define CONFIG_SYS_OSD_SCREENS 1 481 #define CONFIG_SYS_DP501_DIFFERENTIAL 482 #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ 483 484 #ifdef CONFIG_STRIDER_CON_DP 485 #define CONFIG_SYS_OSD_DH 486 #endif 487 488 /* 489 * General PCI 490 * Addresses are mapped 1-1. 491 */ 492 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 493 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 494 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 495 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 496 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 497 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 498 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 499 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 500 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 501 502 /* enable PCIE clock */ 503 #define CONFIG_SYS_SCCR_PCIEXP1CM 1 504 505 #define CONFIG_PCI_INDIRECT_BRIDGE 506 #define CONFIG_PCIE 507 508 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 509 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 510 511 /* 512 * TSEC 513 */ 514 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 515 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 516 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 517 518 /* 519 * TSEC ethernet configuration 520 */ 521 #define CONFIG_MII 1 /* MII PHY management */ 522 #define CONFIG_TSEC1 523 #define CONFIG_TSEC1_NAME "eTSEC0" 524 #define TSEC1_PHY_ADDR 1 525 #define TSEC1_PHYIDX 0 526 #define TSEC1_FLAGS 0 527 528 /* Options are: eTSEC[0-1] */ 529 #define CONFIG_ETHPRIME "eTSEC0" 530 531 /* 532 * Environment 533 */ 534 #if 1 535 #define CONFIG_ENV_IS_IN_FLASH 1 536 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 537 CONFIG_SYS_MONITOR_LEN) 538 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 539 #define CONFIG_ENV_SIZE 0x2000 540 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 541 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 542 #else 543 #define CONFIG_ENV_IS_NOWHERE 544 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 545 #endif 546 547 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 548 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 549 550 /* 551 * Command line configuration. 552 */ 553 #define CONFIG_CMD_PCI 554 555 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 556 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 557 558 /* 559 * Miscellaneous configurable options 560 */ 561 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 562 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 563 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 564 565 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 566 567 /* Print Buffer Size */ 568 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 569 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 570 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 571 572 /* 573 * For booting Linux, the board info and command line data 574 * have to be in the first 256 MB of memory, since this is 575 * the maximum mapped by the Linux kernel during initialization. 576 */ 577 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 578 579 /* 580 * Core HID Setup 581 */ 582 #define CONFIG_SYS_HID0_INIT 0x000000000 583 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 584 HID0_ENABLE_INSTRUCTION_CACHE | \ 585 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 586 #define CONFIG_SYS_HID2 HID2_HBE 587 588 /* 589 * MMU Setup 590 */ 591 592 /* DDR: cache cacheable */ 593 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 594 BATL_MEMCOHERENCE) 595 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ 596 BATU_VS | BATU_VP) 597 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 598 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 599 600 /* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */ 601 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 602 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 603 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ 604 BATU_VP) 605 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 606 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 607 608 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 609 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 610 BATL_MEMCOHERENCE) 611 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ 612 BATU_VS | BATU_VP) 613 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 614 BATL_CACHEINHIBIT | \ 615 BATL_GUARDEDSTORAGE) 616 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 617 618 /* Stack in dcache: cacheable, no memory coherence */ 619 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 620 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 621 BATU_VS | BATU_VP) 622 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 623 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 624 625 /* 626 * Environment Configuration 627 */ 628 629 #define CONFIG_ENV_OVERWRITE 630 631 #if defined(CONFIG_TSEC_ENET) 632 #define CONFIG_HAS_ETH0 633 #endif 634 635 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 636 637 638 #define CONFIG_HOSTNAME hrcon 639 #define CONFIG_ROOTPATH "/opt/nfsroot" 640 #define CONFIG_BOOTFILE "uImage" 641 642 #define CONFIG_PREBOOT /* enable preboot variable */ 643 644 #define CONFIG_EXTRA_ENV_SETTINGS \ 645 "netdev=eth0\0" \ 646 "consoledev=ttyS1\0" \ 647 "u-boot=u-boot.bin\0" \ 648 "kernel_addr=1000000\0" \ 649 "fdt_addr=C00000\0" \ 650 "fdtfile=hrcon.dtb\0" \ 651 "load=tftp ${loadaddr} ${u-boot}\0" \ 652 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 653 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ 654 " +${filesize};cp.b ${fileaddr} " \ 655 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 656 "upd=run load update\0" \ 657 658 #define CONFIG_NFSBOOTCOMMAND \ 659 "setenv bootargs root=/dev/nfs rw " \ 660 "nfsroot=$serverip:$rootpath " \ 661 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 662 "console=$consoledev,$baudrate $othbootargs;" \ 663 "tftp ${kernel_addr} $bootfile;" \ 664 "tftp ${fdt_addr} $fdtfile;" \ 665 "bootm ${kernel_addr} - ${fdt_addr}" 666 667 #define CONFIG_MMCBOOTCOMMAND \ 668 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ 669 "console=$consoledev,$baudrate $othbootargs;" \ 670 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \ 671 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \ 672 "bootm ${kernel_addr} - ${fdt_addr}" 673 674 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND 675 676 #endif /* __CONFIG_H */ 677