1 /* 2 * (C) Copyright 2014 3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de 4 * 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 /* 13 * High Level Configuration Options 14 */ 15 #define CONFIG_E300 1 /* E300 family */ 16 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 17 #define CONFIG_MPC830x 1 /* MPC830x family */ 18 #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ 19 #define CONFIG_STRIDER 1 /* STRIDER board specific */ 20 21 #define CONFIG_SYS_TEXT_BASE 0xFE000000 22 23 #ifdef CONFIG_STRIDER_CPU_DP 24 #define CONFIG_IDENT_STRING " strider cpu dp 0.01" 25 #elif defined(CONFIG_STRIDER_CPU) 26 #define CONFIG_IDENT_STRING " strider cpu 0.01" 27 #elif defined(CONFIG_STRIDER_CON_DP) 28 #define CONFIG_IDENT_STRING " strider con dp 0.01" 29 #else 30 #define CONFIG_IDENT_STRING " strider con 0.01" 31 #endif 32 33 #define CONFIG_BOARD_EARLY_INIT_F 34 #define CONFIG_BOARD_EARLY_INIT_R 35 #define CONFIG_LAST_STAGE_INIT 36 37 #define CONFIG_MMC 38 #define CONFIG_FSL_ESDHC 39 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 40 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 41 42 #define CONFIG_GENERIC_MMC 43 #define CONFIG_DOS_PARTITION 44 45 #define CONFIG_SYS_ALT_MEMTEST 46 47 #define CONFIG_CMD_FPGAD 48 #define CONFIG_CMD_IOLOOP 49 50 /* 51 * System Clock Setup 52 */ 53 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 54 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 55 56 /* 57 * Hardware Reset Configuration Word 58 * if CLKIN is 66.66MHz, then 59 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz 60 * We choose the A type silicon as default, so the core is 400Mhz. 61 */ 62 #define CONFIG_SYS_HRCW_LOW (\ 63 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 64 HRCWL_DDR_TO_SCB_CLK_2X1 |\ 65 HRCWL_SVCOD_DIV_2 |\ 66 HRCWL_CSB_TO_CLKIN_4X1 |\ 67 HRCWL_CORE_TO_CSB_3X1) 68 /* 69 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits 70 * in 8308's HRCWH according to the manual, but original Freescale's 71 * code has them and I've expirienced some problems using the board 72 * with BDI3000 attached when I've tried to set these bits to zero 73 * (UART doesn't work after the 'reset run' command). 74 */ 75 #define CONFIG_SYS_HRCW_HIGH (\ 76 HRCWH_PCI_HOST |\ 77 HRCWH_PCI1_ARBITER_ENABLE |\ 78 HRCWH_CORE_ENABLE |\ 79 HRCWH_FROM_0XFFF00100 |\ 80 HRCWH_BOOTSEQ_DISABLE |\ 81 HRCWH_SW_WATCHDOG_DISABLE |\ 82 HRCWH_ROM_LOC_LOCAL_16BIT |\ 83 HRCWH_RL_EXT_LEGACY |\ 84 HRCWH_TSEC1M_IN_MII |\ 85 HRCWH_TSEC2M_IN_RGMII |\ 86 HRCWH_BIG_ENDIAN) 87 88 /* 89 * System IO Config 90 */ 91 #define CONFIG_SYS_SICRH (\ 92 SICRH_ESDHC_A_SD |\ 93 SICRH_ESDHC_B_SD |\ 94 SICRH_ESDHC_C_SD |\ 95 SICRH_GPIO_A_GPIO |\ 96 SICRH_GPIO_B_GPIO |\ 97 SICRH_IEEE1588_A_GPIO |\ 98 SICRH_USB |\ 99 SICRH_GTM_GPIO |\ 100 SICRH_IEEE1588_B_GPIO |\ 101 SICRH_ETSEC2_GPIO |\ 102 SICRH_GPIOSEL_1 |\ 103 SICRH_TMROBI_V3P3 |\ 104 SICRH_TSOBI1_V2P5 |\ 105 SICRH_TSOBI2_V2P5) /* 0x0037f103 */ 106 #define CONFIG_SYS_SICRL (\ 107 SICRL_SPI_PF0 |\ 108 SICRL_UART_PF0 |\ 109 SICRL_IRQ_PF0 |\ 110 SICRL_I2C2_PF0 |\ 111 SICRL_ETSEC1_TX_CLK) /* 0x00000000 */ 112 113 /* 114 * IMMR new address 115 */ 116 #define CONFIG_SYS_IMMR 0xE0000000 117 118 /* 119 * SERDES 120 */ 121 #define CONFIG_FSL_SERDES 122 #define CONFIG_FSL_SERDES1 0xe3000 123 124 /* 125 * Arbiter Setup 126 */ 127 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 128 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 129 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 130 131 /* 132 * DDR Setup 133 */ 134 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 135 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 136 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 137 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 138 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 139 | DDRCDR_PZ_LOZ \ 140 | DDRCDR_NZ_LOZ \ 141 | DDRCDR_ODT \ 142 | DDRCDR_Q_DRN) 143 /* 0x7b880001 */ 144 /* 145 * Manually set up DDR parameters 146 * consist of one chip NT5TU64M16HG from NANYA 147 */ 148 149 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 150 151 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 152 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 153 | CSCONFIG_ODT_RD_NEVER \ 154 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 155 | CSCONFIG_BANK_BIT_3 \ 156 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 157 /* 0x80010102 */ 158 #define CONFIG_SYS_DDR_TIMING_3 0 159 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 160 | (0 << TIMING_CFG0_WRT_SHIFT) \ 161 | (0 << TIMING_CFG0_RRT_SHIFT) \ 162 | (0 << TIMING_CFG0_WWT_SHIFT) \ 163 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 164 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 165 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 166 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 167 /* 0x00260802 */ 168 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 169 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 170 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 171 | (7 << TIMING_CFG1_CASLAT_SHIFT) \ 172 | (9 << TIMING_CFG1_REFREC_SHIFT) \ 173 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 174 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 175 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 176 /* 0x26279222 */ 177 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ 178 | (4 << TIMING_CFG2_CPO_SHIFT) \ 179 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 180 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 181 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 182 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 183 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 184 /* 0x021848c5 */ 185 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \ 186 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 187 /* 0x08240100 */ 188 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 189 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 190 | SDRAM_CFG_DBW_16) 191 /* 0x43100000 */ 192 193 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 194 #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ 195 | (0x0242 << SDRAM_MODE_SD_SHIFT)) 196 /* ODT 150ohm CL=4, AL=0 on SDRAM */ 197 #define CONFIG_SYS_DDR_MODE2 0x00000000 198 199 /* 200 * Memory test 201 */ 202 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ 203 #define CONFIG_SYS_MEMTEST_END 0x07f00000 204 205 /* 206 * The reserved memory 207 */ 208 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 209 210 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 211 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 212 213 /* 214 * Initial RAM Base Address Setup 215 */ 216 #define CONFIG_SYS_INIT_RAM_LOCK 1 217 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 218 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 219 #define CONFIG_SYS_GBL_DATA_OFFSET \ 220 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 221 222 /* 223 * Local Bus Configuration & Clock Setup 224 */ 225 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 226 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 227 #define CONFIG_SYS_LBC_LBCR 0x00040000 228 229 /* 230 * FLASH on the Local Bus 231 */ 232 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 233 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 234 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 235 #define CONFIG_FLASH_CFI_LEGACY 236 #define CONFIG_SYS_FLASH_LEGACY_512Kx16 237 238 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 239 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ 240 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 241 242 /* Window base at flash base */ 243 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 244 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 245 246 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 247 | BR_PS_16 /* 16 bit port */ \ 248 | BR_MS_GPCM /* MSEL = GPCM */ \ 249 | BR_V) /* valid */ 250 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 251 | OR_UPM_XAM \ 252 | OR_GPCM_CSNT \ 253 | OR_GPCM_ACS_DIV2 \ 254 | OR_GPCM_XACS \ 255 | OR_GPCM_SCY_15 \ 256 | OR_GPCM_TRLX_SET \ 257 | OR_GPCM_EHTR_SET) 258 259 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 260 #define CONFIG_SYS_MAX_FLASH_SECT 135 261 262 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 263 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 264 265 /* 266 * FPGA 267 */ 268 #define CONFIG_SYS_FPGA0_BASE 0xE0600000 269 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ 270 271 /* Window base at FPGA base */ 272 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE 273 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB) 274 275 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \ 276 | BR_PS_16 /* 16 bit port */ \ 277 | BR_MS_GPCM /* MSEL = GPCM */ \ 278 | BR_V) /* valid */ 279 280 #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \ 281 | OR_UPM_XAM \ 282 | OR_GPCM_CSNT \ 283 | OR_GPCM_SCY_5 \ 284 | OR_GPCM_TRLX_CLEAR \ 285 | OR_GPCM_EHTR_CLEAR) 286 287 #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE 288 #define CONFIG_SYS_FPGA_DONE(k) 0x0010 289 290 #define CONFIG_SYS_FPGA_COUNT 1 291 292 #define CONFIG_SYS_MCLINK_MAX 3 293 294 #define CONFIG_SYS_FPGA_PTR \ 295 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL } 296 297 #define CONFIG_SYS_FPGA_NO_RFL_HI 298 299 /* 300 * Serial Port 301 */ 302 #define CONFIG_CONS_INDEX 2 303 #define CONFIG_SYS_NS16550_SERIAL 304 #define CONFIG_SYS_NS16550_REG_SIZE 1 305 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 306 307 #define CONFIG_SYS_BAUDRATE_TABLE \ 308 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 309 310 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 311 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 312 313 /* Pass open firmware flat tree */ 314 315 /* I2C */ 316 #define CONFIG_SYS_I2C 317 #define CONFIG_SYS_I2C_FSL 318 #define CONFIG_SYS_FSL_I2C_SPEED 400000 319 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 320 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 321 322 #define CONFIG_PCA953X /* NXP PCA9554 */ 323 #define CONFIG_CMD_PCA953X 324 #define CONFIG_CMD_PCA953X_INFO 325 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x24, 16}, {0x25, 16}, {0x26, 16}, \ 326 {0x3c, 8}, {0x3d, 8}, {0x3e, 8} } 327 328 #define CONFIG_PCA9698 /* NXP PCA9698 */ 329 330 #define CONFIG_SYS_I2C_IHS 331 #define CONFIG_SYS_I2C_IHS_CH0 332 #define CONFIG_SYS_I2C_IHS_SPEED_0 50000 333 #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F 334 #define CONFIG_SYS_I2C_IHS_CH1 335 #define CONFIG_SYS_I2C_IHS_SPEED_1 50000 336 #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F 337 #define CONFIG_SYS_I2C_IHS_CH2 338 #define CONFIG_SYS_I2C_IHS_SPEED_2 50000 339 #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F 340 #define CONFIG_SYS_I2C_IHS_CH3 341 #define CONFIG_SYS_I2C_IHS_SPEED_3 50000 342 #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F 343 344 #ifdef CONFIG_STRIDER_CON_DP 345 #define CONFIG_SYS_I2C_IHS_DUAL 346 #define CONFIG_SYS_I2C_IHS_CH0_1 347 #define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000 348 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F 349 #define CONFIG_SYS_I2C_IHS_CH1_1 350 #define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000 351 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F 352 #define CONFIG_SYS_I2C_IHS_CH2_1 353 #define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000 354 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F 355 #define CONFIG_SYS_I2C_IHS_CH3_1 356 #define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000 357 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F 358 #endif 359 360 /* 361 * Software (bit-bang) I2C driver configuration 362 */ 363 #define CONFIG_SYS_I2C_SOFT 364 #define CONFIG_SOFT_I2C_READ_REPEATED_START 365 #define CONFIG_SYS_I2C_SOFT_SPEED 50000 366 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F 367 #define I2C_SOFT_DECLARATIONS2 368 #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 369 #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F 370 #define I2C_SOFT_DECLARATIONS3 371 #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000 372 #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F 373 #define I2C_SOFT_DECLARATIONS4 374 #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 375 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F 376 #if defined(CONFIG_STRIDER_CON) || defined(CONFIG_STRIDER_CON_DP) 377 #define I2C_SOFT_DECLARATIONS5 378 #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000 379 #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F 380 #define I2C_SOFT_DECLARATIONS6 381 #define CONFIG_SYS_I2C_SOFT_SPEED_6 50000 382 #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F 383 #define I2C_SOFT_DECLARATIONS7 384 #define CONFIG_SYS_I2C_SOFT_SPEED_7 50000 385 #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F 386 #define I2C_SOFT_DECLARATIONS8 387 #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000 388 #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F 389 #endif 390 #ifdef CONFIG_STRIDER_CON_DP 391 #define I2C_SOFT_DECLARATIONS9 392 #define CONFIG_SYS_I2C_SOFT_SPEED_9 50000 393 #define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F 394 #define I2C_SOFT_DECLARATIONS10 395 #define CONFIG_SYS_I2C_SOFT_SPEED_10 50000 396 #define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F 397 #define I2C_SOFT_DECLARATIONS11 398 #define CONFIG_SYS_I2C_SOFT_SPEED_11 50000 399 #define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F 400 #define I2C_SOFT_DECLARATIONS12 401 #define CONFIG_SYS_I2C_SOFT_SPEED_12 50000 402 #define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F 403 #endif 404 405 #ifdef CONFIG_STRIDER_CON 406 #define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8} 407 #define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8} 408 #define CONFIG_SYS_ADV7611_I2C {5, 6, 7, 8} 409 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 410 #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \ 411 {12, 0x4c} } 412 #elif defined(CONFIG_STRIDER_CON_DP) 413 #define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20} 414 #define CONFIG_SYS_CH7301_I2C {1, 3, 5, 7} 415 #define CONFIG_SYS_ADV7611_I2C {1, 3, 5, 7} 416 #define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8} 417 #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \ 418 {12, 0x4c} } 419 #elif defined(CONFIG_STRIDER_CPU_DP) 420 #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4} 421 #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4} 422 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 423 #define CONFIG_STRIDER_FANS { {6, 0x4c}, {7, 0x4c}, \ 424 {8, 0x4c} } 425 #else 426 #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4} 427 #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4} 428 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 429 #define CONFIG_STRIDER_FANS { {2, 0x18}, {3, 0x18}, \ 430 {4, 0x18} } 431 #endif 432 433 #ifndef __ASSEMBLY__ 434 void fpga_gpio_set(unsigned int bus, int pin); 435 void fpga_gpio_clear(unsigned int bus, int pin); 436 int fpga_gpio_get(unsigned int bus, int pin); 437 void fpga_control_set(unsigned int bus, int pin); 438 void fpga_control_clear(unsigned int bus, int pin); 439 #endif 440 441 #ifdef CONFIG_STRIDER_CON 442 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040) 443 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020) 444 #define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \ 445 (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR) 446 #elif defined(CONFIG_STRIDER_CON_DP) 447 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200) 448 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100) 449 #define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4) 450 #else 451 #define I2C_SDA_GPIO 0x0040 452 #define I2C_SCL_GPIO 0x0020 453 #define I2C_FPGA_IDX I2C_ADAP_HWNR 454 #endif 455 456 #ifdef CONFIG_STRIDER_CON_DP 457 #define I2C_ACTIVE \ 458 do { \ 459 if (I2C_ADAP_HWNR > 7) \ 460 fpga_control_set(I2C_FPGA_IDX, 0x0004); \ 461 else \ 462 fpga_control_clear(I2C_FPGA_IDX, 0x0004); \ 463 } while (0) 464 #else 465 #define I2C_ACTIVE { } 466 #endif 467 468 #define I2C_TRISTATE { } 469 #define I2C_READ \ 470 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0) 471 #define I2C_SDA(bit) \ 472 do { \ 473 if (bit) \ 474 fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \ 475 else \ 476 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \ 477 } while (0) 478 #define I2C_SCL(bit) \ 479 do { \ 480 if (bit) \ 481 fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \ 482 else \ 483 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \ 484 } while (0) 485 #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ 486 487 /* 488 * Software (bit-bang) MII driver configuration 489 */ 490 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 491 #define CONFIG_BITBANGMII_MULTI 492 493 /* 494 * OSD Setup 495 */ 496 #define CONFIG_SYS_OSD_SCREENS 1 497 #define CONFIG_SYS_DP501_DIFFERENTIAL 498 #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ 499 500 #ifdef CONFIG_STRIDER_CON_DP 501 #define CONFIG_SYS_OSD_DH 502 #endif 503 504 /* 505 * General PCI 506 * Addresses are mapped 1-1. 507 */ 508 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 509 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 510 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 511 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 512 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 513 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 514 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 515 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 516 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 517 518 /* enable PCIE clock */ 519 #define CONFIG_SYS_SCCR_PCIEXP1CM 1 520 521 #define CONFIG_PCI 522 #define CONFIG_PCI_INDIRECT_BRIDGE 523 #define CONFIG_PCIE 524 525 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 526 527 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 528 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 529 530 /* 531 * TSEC 532 */ 533 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 534 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 535 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 536 537 /* 538 * TSEC ethernet configuration 539 */ 540 #define CONFIG_MII 1 /* MII PHY management */ 541 #define CONFIG_TSEC1 542 #define CONFIG_TSEC1_NAME "eTSEC0" 543 #define TSEC1_PHY_ADDR 1 544 #define TSEC1_PHYIDX 0 545 #define TSEC1_FLAGS 0 546 547 /* Options are: eTSEC[0-1] */ 548 #define CONFIG_ETHPRIME "eTSEC0" 549 550 /* 551 * Environment 552 */ 553 #if 1 554 #define CONFIG_ENV_IS_IN_FLASH 1 555 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 556 CONFIG_SYS_MONITOR_LEN) 557 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 558 #define CONFIG_ENV_SIZE 0x2000 559 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 560 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 561 #else 562 #define CONFIG_ENV_IS_NOWHERE 563 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 564 #endif 565 566 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 567 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 568 569 /* 570 * Command line configuration. 571 */ 572 #define CONFIG_CMD_PCI 573 574 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 575 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 576 577 /* 578 * Miscellaneous configurable options 579 */ 580 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 581 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 582 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 583 584 #undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ 585 586 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 587 588 #define CONFIG_SYS_CONSOLE_INFO_QUIET 589 590 /* Print Buffer Size */ 591 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 592 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 593 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 594 595 /* 596 * For booting Linux, the board info and command line data 597 * have to be in the first 256 MB of memory, since this is 598 * the maximum mapped by the Linux kernel during initialization. 599 */ 600 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 601 602 /* 603 * Core HID Setup 604 */ 605 #define CONFIG_SYS_HID0_INIT 0x000000000 606 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 607 HID0_ENABLE_INSTRUCTION_CACHE | \ 608 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 609 #define CONFIG_SYS_HID2 HID2_HBE 610 611 /* 612 * MMU Setup 613 */ 614 615 /* DDR: cache cacheable */ 616 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 617 BATL_MEMCOHERENCE) 618 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ 619 BATU_VS | BATU_VP) 620 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 621 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 622 623 /* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */ 624 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 625 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 626 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ 627 BATU_VP) 628 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 629 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 630 631 /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 632 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 633 BATL_MEMCOHERENCE) 634 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ 635 BATU_VS | BATU_VP) 636 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 637 BATL_CACHEINHIBIT | \ 638 BATL_GUARDEDSTORAGE) 639 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 640 641 /* Stack in dcache: cacheable, no memory coherence */ 642 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 643 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 644 BATU_VS | BATU_VP) 645 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 646 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 647 648 /* 649 * Environment Configuration 650 */ 651 652 #define CONFIG_ENV_OVERWRITE 653 654 #if defined(CONFIG_TSEC_ENET) 655 #define CONFIG_HAS_ETH0 656 #endif 657 658 #define CONFIG_BAUDRATE 115200 659 660 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 661 662 663 #define CONFIG_HOSTNAME hrcon 664 #define CONFIG_ROOTPATH "/opt/nfsroot" 665 #define CONFIG_BOOTFILE "uImage" 666 667 #define CONFIG_PREBOOT /* enable preboot variable */ 668 669 #define CONFIG_EXTRA_ENV_SETTINGS \ 670 "netdev=eth0\0" \ 671 "consoledev=ttyS1\0" \ 672 "u-boot=u-boot.bin\0" \ 673 "kernel_addr=1000000\0" \ 674 "fdt_addr=C00000\0" \ 675 "fdtfile=hrcon.dtb\0" \ 676 "load=tftp ${loadaddr} ${u-boot}\0" \ 677 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 678 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ 679 " +${filesize};cp.b ${fileaddr} " \ 680 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 681 "upd=run load update\0" \ 682 683 #define CONFIG_NFSBOOTCOMMAND \ 684 "setenv bootargs root=/dev/nfs rw " \ 685 "nfsroot=$serverip:$rootpath " \ 686 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 687 "console=$consoledev,$baudrate $othbootargs;" \ 688 "tftp ${kernel_addr} $bootfile;" \ 689 "tftp ${fdt_addr} $fdtfile;" \ 690 "bootm ${kernel_addr} - ${fdt_addr}" 691 692 #define CONFIG_MMCBOOTCOMMAND \ 693 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ 694 "console=$consoledev,$baudrate $othbootargs;" \ 695 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \ 696 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \ 697 "bootm ${kernel_addr} - ${fdt_addr}" 698 699 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND 700 701 #endif /* __CONFIG_H */ 702