1*a3f9d6c7SDirk Eibach /* 2*a3f9d6c7SDirk Eibach * (C) Copyright 2014 3*a3f9d6c7SDirk Eibach * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de 4*a3f9d6c7SDirk Eibach * 5*a3f9d6c7SDirk Eibach * 6*a3f9d6c7SDirk Eibach * SPDX-License-Identifier: GPL-2.0+ 7*a3f9d6c7SDirk Eibach */ 8*a3f9d6c7SDirk Eibach 9*a3f9d6c7SDirk Eibach #ifndef __CONFIG_H 10*a3f9d6c7SDirk Eibach #define __CONFIG_H 11*a3f9d6c7SDirk Eibach 12*a3f9d6c7SDirk Eibach /* 13*a3f9d6c7SDirk Eibach * High Level Configuration Options 14*a3f9d6c7SDirk Eibach */ 15*a3f9d6c7SDirk Eibach #define CONFIG_E300 1 /* E300 family */ 16*a3f9d6c7SDirk Eibach #define CONFIG_MPC83xx 1 /* MPC83xx family */ 17*a3f9d6c7SDirk Eibach #define CONFIG_MPC830x 1 /* MPC830x family */ 18*a3f9d6c7SDirk Eibach #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ 19*a3f9d6c7SDirk Eibach #define CONFIG_STRIDER 1 /* STRIDER board specific */ 20*a3f9d6c7SDirk Eibach 21*a3f9d6c7SDirk Eibach #define CONFIG_SYS_TEXT_BASE 0xFE000000 22*a3f9d6c7SDirk Eibach 23*a3f9d6c7SDirk Eibach #ifdef CONFIG_STRIDER_CPU 24*a3f9d6c7SDirk Eibach #define CONFIG_IDENT_STRING " strider cpu 0.01" 25*a3f9d6c7SDirk Eibach #else 26*a3f9d6c7SDirk Eibach #define CONFIG_IDENT_STRING " strider con 0.01" 27*a3f9d6c7SDirk Eibach #endif 28*a3f9d6c7SDirk Eibach 29*a3f9d6c7SDirk Eibach #define CONFIG_BOARD_EARLY_INIT_F 30*a3f9d6c7SDirk Eibach #define CONFIG_BOARD_EARLY_INIT_R 31*a3f9d6c7SDirk Eibach #define CONFIG_LAST_STAGE_INIT 32*a3f9d6c7SDirk Eibach 33*a3f9d6c7SDirk Eibach /* new uImage format support */ 34*a3f9d6c7SDirk Eibach #define CONFIG_FIT 1 35*a3f9d6c7SDirk Eibach #define CONFIG_FIT_VERBOSE 1 36*a3f9d6c7SDirk Eibach 37*a3f9d6c7SDirk Eibach #define CONFIG_MMC 38*a3f9d6c7SDirk Eibach #define CONFIG_FSL_ESDHC 39*a3f9d6c7SDirk Eibach #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 40*a3f9d6c7SDirk Eibach #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 41*a3f9d6c7SDirk Eibach 42*a3f9d6c7SDirk Eibach #define CONFIG_CMD_MMC 43*a3f9d6c7SDirk Eibach #define CONFIG_GENERIC_MMC 44*a3f9d6c7SDirk Eibach #define CONFIG_DOS_PARTITION 45*a3f9d6c7SDirk Eibach #define CONFIG_CMD_EXT2 46*a3f9d6c7SDirk Eibach 47*a3f9d6c7SDirk Eibach #define CONFIG_CMD_MEMTEST 48*a3f9d6c7SDirk Eibach #define CONFIG_SYS_ALT_MEMTEST 49*a3f9d6c7SDirk Eibach 50*a3f9d6c7SDirk Eibach #define CONFIG_CMD_FPGAD 51*a3f9d6c7SDirk Eibach #define CONFIG_CMD_IOLOOP 52*a3f9d6c7SDirk Eibach 53*a3f9d6c7SDirk Eibach /* 54*a3f9d6c7SDirk Eibach * System Clock Setup 55*a3f9d6c7SDirk Eibach */ 56*a3f9d6c7SDirk Eibach #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 57*a3f9d6c7SDirk Eibach #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 58*a3f9d6c7SDirk Eibach 59*a3f9d6c7SDirk Eibach /* 60*a3f9d6c7SDirk Eibach * Hardware Reset Configuration Word 61*a3f9d6c7SDirk Eibach * if CLKIN is 66.66MHz, then 62*a3f9d6c7SDirk Eibach * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz 63*a3f9d6c7SDirk Eibach * We choose the A type silicon as default, so the core is 400Mhz. 64*a3f9d6c7SDirk Eibach */ 65*a3f9d6c7SDirk Eibach #define CONFIG_SYS_HRCW_LOW (\ 66*a3f9d6c7SDirk Eibach HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 67*a3f9d6c7SDirk Eibach HRCWL_DDR_TO_SCB_CLK_2X1 |\ 68*a3f9d6c7SDirk Eibach HRCWL_SVCOD_DIV_2 |\ 69*a3f9d6c7SDirk Eibach HRCWL_CSB_TO_CLKIN_4X1 |\ 70*a3f9d6c7SDirk Eibach HRCWL_CORE_TO_CSB_3X1) 71*a3f9d6c7SDirk Eibach /* 72*a3f9d6c7SDirk Eibach * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits 73*a3f9d6c7SDirk Eibach * in 8308's HRCWH according to the manual, but original Freescale's 74*a3f9d6c7SDirk Eibach * code has them and I've expirienced some problems using the board 75*a3f9d6c7SDirk Eibach * with BDI3000 attached when I've tried to set these bits to zero 76*a3f9d6c7SDirk Eibach * (UART doesn't work after the 'reset run' command). 77*a3f9d6c7SDirk Eibach */ 78*a3f9d6c7SDirk Eibach #define CONFIG_SYS_HRCW_HIGH (\ 79*a3f9d6c7SDirk Eibach HRCWH_PCI_HOST |\ 80*a3f9d6c7SDirk Eibach HRCWH_PCI1_ARBITER_ENABLE |\ 81*a3f9d6c7SDirk Eibach HRCWH_CORE_ENABLE |\ 82*a3f9d6c7SDirk Eibach HRCWH_FROM_0XFFF00100 |\ 83*a3f9d6c7SDirk Eibach HRCWH_BOOTSEQ_DISABLE |\ 84*a3f9d6c7SDirk Eibach HRCWH_SW_WATCHDOG_DISABLE |\ 85*a3f9d6c7SDirk Eibach HRCWH_ROM_LOC_LOCAL_16BIT |\ 86*a3f9d6c7SDirk Eibach HRCWH_RL_EXT_LEGACY |\ 87*a3f9d6c7SDirk Eibach HRCWH_TSEC1M_IN_MII |\ 88*a3f9d6c7SDirk Eibach HRCWH_TSEC2M_IN_RGMII |\ 89*a3f9d6c7SDirk Eibach HRCWH_BIG_ENDIAN) 90*a3f9d6c7SDirk Eibach 91*a3f9d6c7SDirk Eibach /* 92*a3f9d6c7SDirk Eibach * System IO Config 93*a3f9d6c7SDirk Eibach */ 94*a3f9d6c7SDirk Eibach #define CONFIG_SYS_SICRH (\ 95*a3f9d6c7SDirk Eibach SICRH_ESDHC_A_SD |\ 96*a3f9d6c7SDirk Eibach SICRH_ESDHC_B_SD |\ 97*a3f9d6c7SDirk Eibach SICRH_ESDHC_C_SD |\ 98*a3f9d6c7SDirk Eibach SICRH_GPIO_A_GPIO |\ 99*a3f9d6c7SDirk Eibach SICRH_GPIO_B_GPIO |\ 100*a3f9d6c7SDirk Eibach SICRH_IEEE1588_A_GPIO |\ 101*a3f9d6c7SDirk Eibach SICRH_USB |\ 102*a3f9d6c7SDirk Eibach SICRH_GTM_GPIO |\ 103*a3f9d6c7SDirk Eibach SICRH_IEEE1588_B_GPIO |\ 104*a3f9d6c7SDirk Eibach SICRH_ETSEC2_GPIO |\ 105*a3f9d6c7SDirk Eibach SICRH_GPIOSEL_1 |\ 106*a3f9d6c7SDirk Eibach SICRH_TMROBI_V3P3 |\ 107*a3f9d6c7SDirk Eibach SICRH_TSOBI1_V2P5 |\ 108*a3f9d6c7SDirk Eibach SICRH_TSOBI2_V2P5) /* 0x0037f103 */ 109*a3f9d6c7SDirk Eibach #define CONFIG_SYS_SICRL (\ 110*a3f9d6c7SDirk Eibach SICRL_SPI_PF0 |\ 111*a3f9d6c7SDirk Eibach SICRL_UART_PF0 |\ 112*a3f9d6c7SDirk Eibach SICRL_IRQ_PF0 |\ 113*a3f9d6c7SDirk Eibach SICRL_I2C2_PF0 |\ 114*a3f9d6c7SDirk Eibach SICRL_ETSEC1_TX_CLK) /* 0x00000000 */ 115*a3f9d6c7SDirk Eibach 116*a3f9d6c7SDirk Eibach /* 117*a3f9d6c7SDirk Eibach * IMMR new address 118*a3f9d6c7SDirk Eibach */ 119*a3f9d6c7SDirk Eibach #define CONFIG_SYS_IMMR 0xE0000000 120*a3f9d6c7SDirk Eibach 121*a3f9d6c7SDirk Eibach /* 122*a3f9d6c7SDirk Eibach * SERDES 123*a3f9d6c7SDirk Eibach */ 124*a3f9d6c7SDirk Eibach #define CONFIG_FSL_SERDES 125*a3f9d6c7SDirk Eibach #define CONFIG_FSL_SERDES1 0xe3000 126*a3f9d6c7SDirk Eibach 127*a3f9d6c7SDirk Eibach /* 128*a3f9d6c7SDirk Eibach * Arbiter Setup 129*a3f9d6c7SDirk Eibach */ 130*a3f9d6c7SDirk Eibach #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 131*a3f9d6c7SDirk Eibach #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 132*a3f9d6c7SDirk Eibach #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 133*a3f9d6c7SDirk Eibach 134*a3f9d6c7SDirk Eibach /* 135*a3f9d6c7SDirk Eibach * DDR Setup 136*a3f9d6c7SDirk Eibach */ 137*a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 138*a3f9d6c7SDirk Eibach #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 139*a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 140*a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 141*a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 142*a3f9d6c7SDirk Eibach | DDRCDR_PZ_LOZ \ 143*a3f9d6c7SDirk Eibach | DDRCDR_NZ_LOZ \ 144*a3f9d6c7SDirk Eibach | DDRCDR_ODT \ 145*a3f9d6c7SDirk Eibach | DDRCDR_Q_DRN) 146*a3f9d6c7SDirk Eibach /* 0x7b880001 */ 147*a3f9d6c7SDirk Eibach /* 148*a3f9d6c7SDirk Eibach * Manually set up DDR parameters 149*a3f9d6c7SDirk Eibach * consist of one chip NT5TU64M16HG from NANYA 150*a3f9d6c7SDirk Eibach */ 151*a3f9d6c7SDirk Eibach 152*a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 153*a3f9d6c7SDirk Eibach 154*a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 155*a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 156*a3f9d6c7SDirk Eibach | CSCONFIG_ODT_RD_NEVER \ 157*a3f9d6c7SDirk Eibach | CSCONFIG_ODT_WR_ONLY_CURRENT \ 158*a3f9d6c7SDirk Eibach | CSCONFIG_BANK_BIT_3 \ 159*a3f9d6c7SDirk Eibach | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 160*a3f9d6c7SDirk Eibach /* 0x80010102 */ 161*a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_TIMING_3 0 162*a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 163*a3f9d6c7SDirk Eibach | (0 << TIMING_CFG0_WRT_SHIFT) \ 164*a3f9d6c7SDirk Eibach | (0 << TIMING_CFG0_RRT_SHIFT) \ 165*a3f9d6c7SDirk Eibach | (0 << TIMING_CFG0_WWT_SHIFT) \ 166*a3f9d6c7SDirk Eibach | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 167*a3f9d6c7SDirk Eibach | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 168*a3f9d6c7SDirk Eibach | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 169*a3f9d6c7SDirk Eibach | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 170*a3f9d6c7SDirk Eibach /* 0x00260802 */ 171*a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 172*a3f9d6c7SDirk Eibach | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 173*a3f9d6c7SDirk Eibach | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 174*a3f9d6c7SDirk Eibach | (7 << TIMING_CFG1_CASLAT_SHIFT) \ 175*a3f9d6c7SDirk Eibach | (9 << TIMING_CFG1_REFREC_SHIFT) \ 176*a3f9d6c7SDirk Eibach | (2 << TIMING_CFG1_WRREC_SHIFT) \ 177*a3f9d6c7SDirk Eibach | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 178*a3f9d6c7SDirk Eibach | (2 << TIMING_CFG1_WRTORD_SHIFT)) 179*a3f9d6c7SDirk Eibach /* 0x26279222 */ 180*a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ 181*a3f9d6c7SDirk Eibach | (4 << TIMING_CFG2_CPO_SHIFT) \ 182*a3f9d6c7SDirk Eibach | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 183*a3f9d6c7SDirk Eibach | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 184*a3f9d6c7SDirk Eibach | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 185*a3f9d6c7SDirk Eibach | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 186*a3f9d6c7SDirk Eibach | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 187*a3f9d6c7SDirk Eibach /* 0x021848c5 */ 188*a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \ 189*a3f9d6c7SDirk Eibach | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 190*a3f9d6c7SDirk Eibach /* 0x08240100 */ 191*a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 192*a3f9d6c7SDirk Eibach | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 193*a3f9d6c7SDirk Eibach | SDRAM_CFG_DBW_16) 194*a3f9d6c7SDirk Eibach /* 0x43100000 */ 195*a3f9d6c7SDirk Eibach 196*a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 197*a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ 198*a3f9d6c7SDirk Eibach | (0x0242 << SDRAM_MODE_SD_SHIFT)) 199*a3f9d6c7SDirk Eibach /* ODT 150ohm CL=4, AL=0 on SDRAM */ 200*a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_MODE2 0x00000000 201*a3f9d6c7SDirk Eibach 202*a3f9d6c7SDirk Eibach /* 203*a3f9d6c7SDirk Eibach * Memory test 204*a3f9d6c7SDirk Eibach */ 205*a3f9d6c7SDirk Eibach #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ 206*a3f9d6c7SDirk Eibach #define CONFIG_SYS_MEMTEST_END 0x07f00000 207*a3f9d6c7SDirk Eibach 208*a3f9d6c7SDirk Eibach /* 209*a3f9d6c7SDirk Eibach * The reserved memory 210*a3f9d6c7SDirk Eibach */ 211*a3f9d6c7SDirk Eibach #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 212*a3f9d6c7SDirk Eibach 213*a3f9d6c7SDirk Eibach #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 214*a3f9d6c7SDirk Eibach #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 215*a3f9d6c7SDirk Eibach 216*a3f9d6c7SDirk Eibach /* 217*a3f9d6c7SDirk Eibach * Initial RAM Base Address Setup 218*a3f9d6c7SDirk Eibach */ 219*a3f9d6c7SDirk Eibach #define CONFIG_SYS_INIT_RAM_LOCK 1 220*a3f9d6c7SDirk Eibach #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 221*a3f9d6c7SDirk Eibach #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 222*a3f9d6c7SDirk Eibach #define CONFIG_SYS_GBL_DATA_OFFSET \ 223*a3f9d6c7SDirk Eibach (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 224*a3f9d6c7SDirk Eibach 225*a3f9d6c7SDirk Eibach /* 226*a3f9d6c7SDirk Eibach * Local Bus Configuration & Clock Setup 227*a3f9d6c7SDirk Eibach */ 228*a3f9d6c7SDirk Eibach #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 229*a3f9d6c7SDirk Eibach #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 230*a3f9d6c7SDirk Eibach #define CONFIG_SYS_LBC_LBCR 0x00040000 231*a3f9d6c7SDirk Eibach 232*a3f9d6c7SDirk Eibach /* 233*a3f9d6c7SDirk Eibach * FLASH on the Local Bus 234*a3f9d6c7SDirk Eibach */ 235*a3f9d6c7SDirk Eibach #if 1 236*a3f9d6c7SDirk Eibach #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 237*a3f9d6c7SDirk Eibach #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 238*a3f9d6c7SDirk Eibach #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 239*a3f9d6c7SDirk Eibach #define CONFIG_FLASH_CFI_LEGACY 240*a3f9d6c7SDirk Eibach #define CONFIG_SYS_FLASH_LEGACY_512Kx16 241*a3f9d6c7SDirk Eibach #else 242*a3f9d6c7SDirk Eibach #define CONFIG_SYS_NO_FLASH 243*a3f9d6c7SDirk Eibach #endif 244*a3f9d6c7SDirk Eibach 245*a3f9d6c7SDirk Eibach #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 246*a3f9d6c7SDirk Eibach #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ 247*a3f9d6c7SDirk Eibach #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 248*a3f9d6c7SDirk Eibach 249*a3f9d6c7SDirk Eibach /* Window base at flash base */ 250*a3f9d6c7SDirk Eibach #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 251*a3f9d6c7SDirk Eibach #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 252*a3f9d6c7SDirk Eibach 253*a3f9d6c7SDirk Eibach #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 254*a3f9d6c7SDirk Eibach | BR_PS_16 /* 16 bit port */ \ 255*a3f9d6c7SDirk Eibach | BR_MS_GPCM /* MSEL = GPCM */ \ 256*a3f9d6c7SDirk Eibach | BR_V) /* valid */ 257*a3f9d6c7SDirk Eibach #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 258*a3f9d6c7SDirk Eibach | OR_UPM_XAM \ 259*a3f9d6c7SDirk Eibach | OR_GPCM_CSNT \ 260*a3f9d6c7SDirk Eibach | OR_GPCM_ACS_DIV2 \ 261*a3f9d6c7SDirk Eibach | OR_GPCM_XACS \ 262*a3f9d6c7SDirk Eibach | OR_GPCM_SCY_15 \ 263*a3f9d6c7SDirk Eibach | OR_GPCM_TRLX_SET \ 264*a3f9d6c7SDirk Eibach | OR_GPCM_EHTR_SET) 265*a3f9d6c7SDirk Eibach 266*a3f9d6c7SDirk Eibach #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 267*a3f9d6c7SDirk Eibach #define CONFIG_SYS_MAX_FLASH_SECT 135 268*a3f9d6c7SDirk Eibach 269*a3f9d6c7SDirk Eibach #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 270*a3f9d6c7SDirk Eibach #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 271*a3f9d6c7SDirk Eibach 272*a3f9d6c7SDirk Eibach /* 273*a3f9d6c7SDirk Eibach * FPGA 274*a3f9d6c7SDirk Eibach */ 275*a3f9d6c7SDirk Eibach #define CONFIG_SYS_FPGA0_BASE 0xE0600000 276*a3f9d6c7SDirk Eibach #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ 277*a3f9d6c7SDirk Eibach 278*a3f9d6c7SDirk Eibach /* Window base at FPGA base */ 279*a3f9d6c7SDirk Eibach #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE 280*a3f9d6c7SDirk Eibach #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB) 281*a3f9d6c7SDirk Eibach 282*a3f9d6c7SDirk Eibach #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \ 283*a3f9d6c7SDirk Eibach | BR_PS_16 /* 16 bit port */ \ 284*a3f9d6c7SDirk Eibach | BR_MS_GPCM /* MSEL = GPCM */ \ 285*a3f9d6c7SDirk Eibach | BR_V) /* valid */ 286*a3f9d6c7SDirk Eibach #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \ 287*a3f9d6c7SDirk Eibach | OR_UPM_XAM \ 288*a3f9d6c7SDirk Eibach | OR_GPCM_CSNT \ 289*a3f9d6c7SDirk Eibach | OR_GPCM_ACS_DIV2 \ 290*a3f9d6c7SDirk Eibach | OR_GPCM_XACS \ 291*a3f9d6c7SDirk Eibach | OR_GPCM_SCY_15 \ 292*a3f9d6c7SDirk Eibach | OR_GPCM_TRLX_SET \ 293*a3f9d6c7SDirk Eibach | OR_GPCM_EHTR_SET) 294*a3f9d6c7SDirk Eibach 295*a3f9d6c7SDirk Eibach #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE 296*a3f9d6c7SDirk Eibach #define CONFIG_SYS_FPGA_DONE(k) 0x0010 297*a3f9d6c7SDirk Eibach 298*a3f9d6c7SDirk Eibach #define CONFIG_SYS_FPGA_COUNT 1 299*a3f9d6c7SDirk Eibach 300*a3f9d6c7SDirk Eibach #define CONFIG_SYS_MCLINK_MAX 3 301*a3f9d6c7SDirk Eibach 302*a3f9d6c7SDirk Eibach #define CONFIG_SYS_FPGA_PTR \ 303*a3f9d6c7SDirk Eibach { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL } 304*a3f9d6c7SDirk Eibach 305*a3f9d6c7SDirk Eibach #define CONFIG_SYS_FPGA_NO_RFL_HI 306*a3f9d6c7SDirk Eibach 307*a3f9d6c7SDirk Eibach /* 308*a3f9d6c7SDirk Eibach * Serial Port 309*a3f9d6c7SDirk Eibach */ 310*a3f9d6c7SDirk Eibach #define CONFIG_CONS_INDEX 2 311*a3f9d6c7SDirk Eibach #define CONFIG_SYS_NS16550 312*a3f9d6c7SDirk Eibach #define CONFIG_SYS_NS16550_SERIAL 313*a3f9d6c7SDirk Eibach #define CONFIG_SYS_NS16550_REG_SIZE 1 314*a3f9d6c7SDirk Eibach #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 315*a3f9d6c7SDirk Eibach 316*a3f9d6c7SDirk Eibach #define CONFIG_SYS_BAUDRATE_TABLE \ 317*a3f9d6c7SDirk Eibach {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 318*a3f9d6c7SDirk Eibach 319*a3f9d6c7SDirk Eibach #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 320*a3f9d6c7SDirk Eibach #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 321*a3f9d6c7SDirk Eibach 322*a3f9d6c7SDirk Eibach /* Use the HUSH parser */ 323*a3f9d6c7SDirk Eibach #define CONFIG_SYS_HUSH_PARSER 324*a3f9d6c7SDirk Eibach 325*a3f9d6c7SDirk Eibach /* Pass open firmware flat tree */ 326*a3f9d6c7SDirk Eibach #define CONFIG_OF_LIBFDT 1 327*a3f9d6c7SDirk Eibach #define CONFIG_OF_BOARD_SETUP 1 328*a3f9d6c7SDirk Eibach #define CONFIG_OF_STDOUT_VIA_ALIAS 1 329*a3f9d6c7SDirk Eibach 330*a3f9d6c7SDirk Eibach /* I2C */ 331*a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C 332*a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_FSL 333*a3f9d6c7SDirk Eibach #define CONFIG_SYS_FSL_I2C_SPEED 400000 334*a3f9d6c7SDirk Eibach #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 335*a3f9d6c7SDirk Eibach #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 336*a3f9d6c7SDirk Eibach 337*a3f9d6c7SDirk Eibach #define CONFIG_PCA953X /* NXP PCA9554 */ 338*a3f9d6c7SDirk Eibach #define CONFIG_PCA9698 /* NXP PCA9698 */ 339*a3f9d6c7SDirk Eibach 340*a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS 341*a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS_CH0 342*a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS_SPEED_0 50000 343*a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F 344*a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS_CH1 345*a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS_SPEED_1 50000 346*a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F 347*a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS_CH2 348*a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS_SPEED_2 50000 349*a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F 350*a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS_CH3 351*a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS_SPEED_3 50000 352*a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F 353*a3f9d6c7SDirk Eibach 354*a3f9d6c7SDirk Eibach /* 355*a3f9d6c7SDirk Eibach * Software (bit-bang) I2C driver configuration 356*a3f9d6c7SDirk Eibach */ 357*a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT 358*a3f9d6c7SDirk Eibach #define CONFIG_SOFT_I2C_READ_REPEATED_START 359*a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SPEED 50000 360*a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F 361*a3f9d6c7SDirk Eibach #define I2C_SOFT_DECLARATIONS2 362*a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 363*a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F 364*a3f9d6c7SDirk Eibach #define I2C_SOFT_DECLARATIONS3 365*a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000 366*a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F 367*a3f9d6c7SDirk Eibach #define I2C_SOFT_DECLARATIONS4 368*a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 369*a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F 370*a3f9d6c7SDirk Eibach #ifdef CONFIG_STRIDER_CON 371*a3f9d6c7SDirk Eibach #define I2C_SOFT_DECLARATIONS5 372*a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000 373*a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F 374*a3f9d6c7SDirk Eibach #define I2C_SOFT_DECLARATIONS6 375*a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SPEED_6 50000 376*a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F 377*a3f9d6c7SDirk Eibach #define I2C_SOFT_DECLARATIONS7 378*a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SPEED_7 50000 379*a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F 380*a3f9d6c7SDirk Eibach #define I2C_SOFT_DECLARATIONS8 381*a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000 382*a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F 383*a3f9d6c7SDirk Eibach #endif 384*a3f9d6c7SDirk Eibach 385*a3f9d6c7SDirk Eibach #ifdef CONFIG_STRIDER_CON 386*a3f9d6c7SDirk Eibach #define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8} 387*a3f9d6c7SDirk Eibach #define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8} 388*a3f9d6c7SDirk Eibach #define CONFIG_SYS_ADV7611_I2C {5, 6, 7, 8} 389*a3f9d6c7SDirk Eibach #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 390*a3f9d6c7SDirk Eibach #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \ 391*a3f9d6c7SDirk Eibach {12, 0x4c} } 392*a3f9d6c7SDirk Eibach #else 393*a3f9d6c7SDirk Eibach #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4} 394*a3f9d6c7SDirk Eibach #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4} 395*a3f9d6c7SDirk Eibach #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 396*a3f9d6c7SDirk Eibach #define CONFIG_STRIDER_FANS { {2, 0x18}, {3, 0x18}, \ 397*a3f9d6c7SDirk Eibach {4, 0x18} } 398*a3f9d6c7SDirk Eibach #endif 399*a3f9d6c7SDirk Eibach 400*a3f9d6c7SDirk Eibach #ifndef __ASSEMBLY__ 401*a3f9d6c7SDirk Eibach void fpga_gpio_set(unsigned int bus, int pin); 402*a3f9d6c7SDirk Eibach void fpga_gpio_clear(unsigned int bus, int pin); 403*a3f9d6c7SDirk Eibach int fpga_gpio_get(unsigned int bus, int pin); 404*a3f9d6c7SDirk Eibach #endif 405*a3f9d6c7SDirk Eibach 406*a3f9d6c7SDirk Eibach #ifdef CONFIG_STRIDER_CON 407*a3f9d6c7SDirk Eibach #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040) 408*a3f9d6c7SDirk Eibach #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020) 409*a3f9d6c7SDirk Eibach #define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \ 410*a3f9d6c7SDirk Eibach (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR) 411*a3f9d6c7SDirk Eibach #else 412*a3f9d6c7SDirk Eibach #define I2C_SDA_GPIO 0x0040 413*a3f9d6c7SDirk Eibach #define I2C_SCL_GPIO 0x0020 414*a3f9d6c7SDirk Eibach #define I2C_FPGA_IDX I2C_ADAP_HWNR 415*a3f9d6c7SDirk Eibach #endif 416*a3f9d6c7SDirk Eibach #define I2C_ACTIVE { } 417*a3f9d6c7SDirk Eibach #define I2C_TRISTATE { } 418*a3f9d6c7SDirk Eibach #define I2C_READ \ 419*a3f9d6c7SDirk Eibach (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0) 420*a3f9d6c7SDirk Eibach #define I2C_SDA(bit) \ 421*a3f9d6c7SDirk Eibach do { \ 422*a3f9d6c7SDirk Eibach if (bit) \ 423*a3f9d6c7SDirk Eibach fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \ 424*a3f9d6c7SDirk Eibach else \ 425*a3f9d6c7SDirk Eibach fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \ 426*a3f9d6c7SDirk Eibach } while (0) 427*a3f9d6c7SDirk Eibach #define I2C_SCL(bit) \ 428*a3f9d6c7SDirk Eibach do { \ 429*a3f9d6c7SDirk Eibach if (bit) \ 430*a3f9d6c7SDirk Eibach fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \ 431*a3f9d6c7SDirk Eibach else \ 432*a3f9d6c7SDirk Eibach fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \ 433*a3f9d6c7SDirk Eibach } while (0) 434*a3f9d6c7SDirk Eibach #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ 435*a3f9d6c7SDirk Eibach 436*a3f9d6c7SDirk Eibach /* 437*a3f9d6c7SDirk Eibach * Software (bit-bang) MII driver configuration 438*a3f9d6c7SDirk Eibach */ 439*a3f9d6c7SDirk Eibach #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 440*a3f9d6c7SDirk Eibach #define CONFIG_BITBANGMII_MULTI 441*a3f9d6c7SDirk Eibach 442*a3f9d6c7SDirk Eibach /* 443*a3f9d6c7SDirk Eibach * OSD Setup 444*a3f9d6c7SDirk Eibach */ 445*a3f9d6c7SDirk Eibach #define CONFIG_SYS_OSD_SCREENS 1 446*a3f9d6c7SDirk Eibach #define CONFIG_SYS_DP501_DIFFERENTIAL 447*a3f9d6c7SDirk Eibach #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ 448*a3f9d6c7SDirk Eibach 449*a3f9d6c7SDirk Eibach /* 450*a3f9d6c7SDirk Eibach * General PCI 451*a3f9d6c7SDirk Eibach * Addresses are mapped 1-1. 452*a3f9d6c7SDirk Eibach */ 453*a3f9d6c7SDirk Eibach #define CONFIG_SYS_PCIE1_BASE 0xA0000000 454*a3f9d6c7SDirk Eibach #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 455*a3f9d6c7SDirk Eibach #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 456*a3f9d6c7SDirk Eibach #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 457*a3f9d6c7SDirk Eibach #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 458*a3f9d6c7SDirk Eibach #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 459*a3f9d6c7SDirk Eibach #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 460*a3f9d6c7SDirk Eibach #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 461*a3f9d6c7SDirk Eibach #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 462*a3f9d6c7SDirk Eibach 463*a3f9d6c7SDirk Eibach /* enable PCIE clock */ 464*a3f9d6c7SDirk Eibach #define CONFIG_SYS_SCCR_PCIEXP1CM 1 465*a3f9d6c7SDirk Eibach 466*a3f9d6c7SDirk Eibach #define CONFIG_PCI 467*a3f9d6c7SDirk Eibach #define CONFIG_PCI_INDIRECT_BRIDGE 468*a3f9d6c7SDirk Eibach #define CONFIG_PCIE 469*a3f9d6c7SDirk Eibach 470*a3f9d6c7SDirk Eibach #define CONFIG_PCI_PNP /* do pci plug-and-play */ 471*a3f9d6c7SDirk Eibach 472*a3f9d6c7SDirk Eibach #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 473*a3f9d6c7SDirk Eibach #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 474*a3f9d6c7SDirk Eibach 475*a3f9d6c7SDirk Eibach /* 476*a3f9d6c7SDirk Eibach * TSEC 477*a3f9d6c7SDirk Eibach */ 478*a3f9d6c7SDirk Eibach #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 479*a3f9d6c7SDirk Eibach #define CONFIG_SYS_TSEC1_OFFSET 0x24000 480*a3f9d6c7SDirk Eibach #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 481*a3f9d6c7SDirk Eibach 482*a3f9d6c7SDirk Eibach /* 483*a3f9d6c7SDirk Eibach * TSEC ethernet configuration 484*a3f9d6c7SDirk Eibach */ 485*a3f9d6c7SDirk Eibach #define CONFIG_MII 1 /* MII PHY management */ 486*a3f9d6c7SDirk Eibach #define CONFIG_TSEC1 487*a3f9d6c7SDirk Eibach #define CONFIG_TSEC1_NAME "eTSEC0" 488*a3f9d6c7SDirk Eibach #define TSEC1_PHY_ADDR 1 489*a3f9d6c7SDirk Eibach #define TSEC1_PHYIDX 0 490*a3f9d6c7SDirk Eibach #define TSEC1_FLAGS 0 491*a3f9d6c7SDirk Eibach 492*a3f9d6c7SDirk Eibach /* Options are: eTSEC[0-1] */ 493*a3f9d6c7SDirk Eibach #define CONFIG_ETHPRIME "eTSEC0" 494*a3f9d6c7SDirk Eibach 495*a3f9d6c7SDirk Eibach /* 496*a3f9d6c7SDirk Eibach * Environment 497*a3f9d6c7SDirk Eibach */ 498*a3f9d6c7SDirk Eibach #if 1 499*a3f9d6c7SDirk Eibach #define CONFIG_ENV_IS_IN_FLASH 1 500*a3f9d6c7SDirk Eibach #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 501*a3f9d6c7SDirk Eibach CONFIG_SYS_MONITOR_LEN) 502*a3f9d6c7SDirk Eibach #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 503*a3f9d6c7SDirk Eibach #define CONFIG_ENV_SIZE 0x2000 504*a3f9d6c7SDirk Eibach #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 505*a3f9d6c7SDirk Eibach #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 506*a3f9d6c7SDirk Eibach #else 507*a3f9d6c7SDirk Eibach #define CONFIG_ENV_IS_NOWHERE 508*a3f9d6c7SDirk Eibach #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 509*a3f9d6c7SDirk Eibach #endif 510*a3f9d6c7SDirk Eibach 511*a3f9d6c7SDirk Eibach #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 512*a3f9d6c7SDirk Eibach #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 513*a3f9d6c7SDirk Eibach 514*a3f9d6c7SDirk Eibach /* 515*a3f9d6c7SDirk Eibach * Command line configuration. 516*a3f9d6c7SDirk Eibach */ 517*a3f9d6c7SDirk Eibach #define CONFIG_CMD_I2C 518*a3f9d6c7SDirk Eibach #define CONFIG_CMD_MII 519*a3f9d6c7SDirk Eibach #define CONFIG_CMD_PCI 520*a3f9d6c7SDirk Eibach #define CONFIG_CMD_PING 521*a3f9d6c7SDirk Eibach 522*a3f9d6c7SDirk Eibach #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 523*a3f9d6c7SDirk Eibach #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 524*a3f9d6c7SDirk Eibach 525*a3f9d6c7SDirk Eibach /* 526*a3f9d6c7SDirk Eibach * Miscellaneous configurable options 527*a3f9d6c7SDirk Eibach */ 528*a3f9d6c7SDirk Eibach #define CONFIG_SYS_LONGHELP /* undef to save memory */ 529*a3f9d6c7SDirk Eibach #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 530*a3f9d6c7SDirk Eibach #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 531*a3f9d6c7SDirk Eibach 532*a3f9d6c7SDirk Eibach #undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ 533*a3f9d6c7SDirk Eibach 534*a3f9d6c7SDirk Eibach #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 535*a3f9d6c7SDirk Eibach 536*a3f9d6c7SDirk Eibach #define CONFIG_SYS_CONSOLE_INFO_QUIET 537*a3f9d6c7SDirk Eibach 538*a3f9d6c7SDirk Eibach /* Print Buffer Size */ 539*a3f9d6c7SDirk Eibach #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 540*a3f9d6c7SDirk Eibach #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 541*a3f9d6c7SDirk Eibach #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 542*a3f9d6c7SDirk Eibach 543*a3f9d6c7SDirk Eibach /* 544*a3f9d6c7SDirk Eibach * For booting Linux, the board info and command line data 545*a3f9d6c7SDirk Eibach * have to be in the first 256 MB of memory, since this is 546*a3f9d6c7SDirk Eibach * the maximum mapped by the Linux kernel during initialization. 547*a3f9d6c7SDirk Eibach */ 548*a3f9d6c7SDirk Eibach #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 549*a3f9d6c7SDirk Eibach 550*a3f9d6c7SDirk Eibach /* 551*a3f9d6c7SDirk Eibach * Core HID Setup 552*a3f9d6c7SDirk Eibach */ 553*a3f9d6c7SDirk Eibach #define CONFIG_SYS_HID0_INIT 0x000000000 554*a3f9d6c7SDirk Eibach #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 555*a3f9d6c7SDirk Eibach HID0_ENABLE_INSTRUCTION_CACHE | \ 556*a3f9d6c7SDirk Eibach HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 557*a3f9d6c7SDirk Eibach #define CONFIG_SYS_HID2 HID2_HBE 558*a3f9d6c7SDirk Eibach 559*a3f9d6c7SDirk Eibach /* 560*a3f9d6c7SDirk Eibach * MMU Setup 561*a3f9d6c7SDirk Eibach */ 562*a3f9d6c7SDirk Eibach 563*a3f9d6c7SDirk Eibach /* DDR: cache cacheable */ 564*a3f9d6c7SDirk Eibach #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 565*a3f9d6c7SDirk Eibach BATL_MEMCOHERENCE) 566*a3f9d6c7SDirk Eibach #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ 567*a3f9d6c7SDirk Eibach BATU_VS | BATU_VP) 568*a3f9d6c7SDirk Eibach #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 569*a3f9d6c7SDirk Eibach #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 570*a3f9d6c7SDirk Eibach 571*a3f9d6c7SDirk Eibach /* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */ 572*a3f9d6c7SDirk Eibach #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 573*a3f9d6c7SDirk Eibach BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 574*a3f9d6c7SDirk Eibach #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ 575*a3f9d6c7SDirk Eibach BATU_VP) 576*a3f9d6c7SDirk Eibach #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 577*a3f9d6c7SDirk Eibach #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 578*a3f9d6c7SDirk Eibach 579*a3f9d6c7SDirk Eibach /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 580*a3f9d6c7SDirk Eibach #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 581*a3f9d6c7SDirk Eibach BATL_MEMCOHERENCE) 582*a3f9d6c7SDirk Eibach #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ 583*a3f9d6c7SDirk Eibach BATU_VS | BATU_VP) 584*a3f9d6c7SDirk Eibach #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 585*a3f9d6c7SDirk Eibach BATL_CACHEINHIBIT | \ 586*a3f9d6c7SDirk Eibach BATL_GUARDEDSTORAGE) 587*a3f9d6c7SDirk Eibach #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 588*a3f9d6c7SDirk Eibach 589*a3f9d6c7SDirk Eibach /* Stack in dcache: cacheable, no memory coherence */ 590*a3f9d6c7SDirk Eibach #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 591*a3f9d6c7SDirk Eibach #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 592*a3f9d6c7SDirk Eibach BATU_VS | BATU_VP) 593*a3f9d6c7SDirk Eibach #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 594*a3f9d6c7SDirk Eibach #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 595*a3f9d6c7SDirk Eibach 596*a3f9d6c7SDirk Eibach /* 597*a3f9d6c7SDirk Eibach * Environment Configuration 598*a3f9d6c7SDirk Eibach */ 599*a3f9d6c7SDirk Eibach 600*a3f9d6c7SDirk Eibach #define CONFIG_ENV_OVERWRITE 601*a3f9d6c7SDirk Eibach 602*a3f9d6c7SDirk Eibach #if defined(CONFIG_TSEC_ENET) 603*a3f9d6c7SDirk Eibach #define CONFIG_HAS_ETH0 604*a3f9d6c7SDirk Eibach #endif 605*a3f9d6c7SDirk Eibach 606*a3f9d6c7SDirk Eibach #define CONFIG_BAUDRATE 115200 607*a3f9d6c7SDirk Eibach 608*a3f9d6c7SDirk Eibach #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 609*a3f9d6c7SDirk Eibach 610*a3f9d6c7SDirk Eibach #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ 611*a3f9d6c7SDirk Eibach 612*a3f9d6c7SDirk Eibach #define CONFIG_HOSTNAME hrcon 613*a3f9d6c7SDirk Eibach #define CONFIG_ROOTPATH "/opt/nfsroot" 614*a3f9d6c7SDirk Eibach #define CONFIG_BOOTFILE "uImage" 615*a3f9d6c7SDirk Eibach 616*a3f9d6c7SDirk Eibach #define CONFIG_PREBOOT /* enable preboot variable */ 617*a3f9d6c7SDirk Eibach 618*a3f9d6c7SDirk Eibach #define CONFIG_EXTRA_ENV_SETTINGS \ 619*a3f9d6c7SDirk Eibach "netdev=eth0\0" \ 620*a3f9d6c7SDirk Eibach "consoledev=ttyS1\0" \ 621*a3f9d6c7SDirk Eibach "u-boot=u-boot.bin\0" \ 622*a3f9d6c7SDirk Eibach "kernel_addr=1000000\0" \ 623*a3f9d6c7SDirk Eibach "fdt_addr=C00000\0" \ 624*a3f9d6c7SDirk Eibach "fdtfile=hrcon.dtb\0" \ 625*a3f9d6c7SDirk Eibach "load=tftp ${loadaddr} ${u-boot}\0" \ 626*a3f9d6c7SDirk Eibach "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 627*a3f9d6c7SDirk Eibach " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ 628*a3f9d6c7SDirk Eibach " +${filesize};cp.b ${fileaddr} " \ 629*a3f9d6c7SDirk Eibach __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 630*a3f9d6c7SDirk Eibach "upd=run load update\0" \ 631*a3f9d6c7SDirk Eibach 632*a3f9d6c7SDirk Eibach #define CONFIG_NFSBOOTCOMMAND \ 633*a3f9d6c7SDirk Eibach "setenv bootargs root=/dev/nfs rw " \ 634*a3f9d6c7SDirk Eibach "nfsroot=$serverip:$rootpath " \ 635*a3f9d6c7SDirk Eibach "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 636*a3f9d6c7SDirk Eibach "console=$consoledev,$baudrate $othbootargs;" \ 637*a3f9d6c7SDirk Eibach "tftp ${kernel_addr} $bootfile;" \ 638*a3f9d6c7SDirk Eibach "tftp ${fdt_addr} $fdtfile;" \ 639*a3f9d6c7SDirk Eibach "bootm ${kernel_addr} - ${fdt_addr}" 640*a3f9d6c7SDirk Eibach 641*a3f9d6c7SDirk Eibach #define CONFIG_MMCBOOTCOMMAND \ 642*a3f9d6c7SDirk Eibach "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ 643*a3f9d6c7SDirk Eibach "console=$consoledev,$baudrate $othbootargs;" \ 644*a3f9d6c7SDirk Eibach "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \ 645*a3f9d6c7SDirk Eibach "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \ 646*a3f9d6c7SDirk Eibach "bootm ${kernel_addr} - ${fdt_addr}" 647*a3f9d6c7SDirk Eibach 648*a3f9d6c7SDirk Eibach #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND 649*a3f9d6c7SDirk Eibach 650*a3f9d6c7SDirk Eibach 651*a3f9d6c7SDirk Eibach #endif /* __CONFIG_H */ 652