1a3f9d6c7SDirk Eibach /* 2a3f9d6c7SDirk Eibach * (C) Copyright 2014 3a3f9d6c7SDirk Eibach * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de 4a3f9d6c7SDirk Eibach * 5a3f9d6c7SDirk Eibach * 6a3f9d6c7SDirk Eibach * SPDX-License-Identifier: GPL-2.0+ 7a3f9d6c7SDirk Eibach */ 8a3f9d6c7SDirk Eibach 9a3f9d6c7SDirk Eibach #ifndef __CONFIG_H 10a3f9d6c7SDirk Eibach #define __CONFIG_H 11a3f9d6c7SDirk Eibach 12a3f9d6c7SDirk Eibach /* 13a3f9d6c7SDirk Eibach * High Level Configuration Options 14a3f9d6c7SDirk Eibach */ 15a3f9d6c7SDirk Eibach #define CONFIG_E300 1 /* E300 family */ 16a3f9d6c7SDirk Eibach #define CONFIG_MPC83xx 1 /* MPC83xx family */ 17a3f9d6c7SDirk Eibach #define CONFIG_MPC830x 1 /* MPC830x family */ 18a3f9d6c7SDirk Eibach #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ 19a3f9d6c7SDirk Eibach #define CONFIG_STRIDER 1 /* STRIDER board specific */ 20a3f9d6c7SDirk Eibach 21a3f9d6c7SDirk Eibach #define CONFIG_SYS_TEXT_BASE 0xFE000000 22a3f9d6c7SDirk Eibach 23a3f9d6c7SDirk Eibach #ifdef CONFIG_STRIDER_CPU 24a3f9d6c7SDirk Eibach #define CONFIG_IDENT_STRING " strider cpu 0.01" 25a3f9d6c7SDirk Eibach #else 26a3f9d6c7SDirk Eibach #define CONFIG_IDENT_STRING " strider con 0.01" 27a3f9d6c7SDirk Eibach #endif 28a3f9d6c7SDirk Eibach 29a3f9d6c7SDirk Eibach #define CONFIG_BOARD_EARLY_INIT_F 30a3f9d6c7SDirk Eibach #define CONFIG_BOARD_EARLY_INIT_R 31a3f9d6c7SDirk Eibach #define CONFIG_LAST_STAGE_INIT 32a3f9d6c7SDirk Eibach 33a3f9d6c7SDirk Eibach #define CONFIG_MMC 34a3f9d6c7SDirk Eibach #define CONFIG_FSL_ESDHC 35a3f9d6c7SDirk Eibach #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 36a3f9d6c7SDirk Eibach #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 37a3f9d6c7SDirk Eibach 38a3f9d6c7SDirk Eibach #define CONFIG_CMD_MMC 39a3f9d6c7SDirk Eibach #define CONFIG_GENERIC_MMC 40a3f9d6c7SDirk Eibach #define CONFIG_DOS_PARTITION 41a3f9d6c7SDirk Eibach #define CONFIG_CMD_EXT2 42a3f9d6c7SDirk Eibach 43a3f9d6c7SDirk Eibach #define CONFIG_CMD_MEMTEST 44a3f9d6c7SDirk Eibach #define CONFIG_SYS_ALT_MEMTEST 45a3f9d6c7SDirk Eibach 46a3f9d6c7SDirk Eibach #define CONFIG_CMD_FPGAD 47a3f9d6c7SDirk Eibach #define CONFIG_CMD_IOLOOP 48a3f9d6c7SDirk Eibach 49a3f9d6c7SDirk Eibach /* 50a3f9d6c7SDirk Eibach * System Clock Setup 51a3f9d6c7SDirk Eibach */ 52a3f9d6c7SDirk Eibach #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 53a3f9d6c7SDirk Eibach #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 54a3f9d6c7SDirk Eibach 55a3f9d6c7SDirk Eibach /* 56a3f9d6c7SDirk Eibach * Hardware Reset Configuration Word 57a3f9d6c7SDirk Eibach * if CLKIN is 66.66MHz, then 58a3f9d6c7SDirk Eibach * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz 59a3f9d6c7SDirk Eibach * We choose the A type silicon as default, so the core is 400Mhz. 60a3f9d6c7SDirk Eibach */ 61a3f9d6c7SDirk Eibach #define CONFIG_SYS_HRCW_LOW (\ 62a3f9d6c7SDirk Eibach HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 63a3f9d6c7SDirk Eibach HRCWL_DDR_TO_SCB_CLK_2X1 |\ 64a3f9d6c7SDirk Eibach HRCWL_SVCOD_DIV_2 |\ 65a3f9d6c7SDirk Eibach HRCWL_CSB_TO_CLKIN_4X1 |\ 66a3f9d6c7SDirk Eibach HRCWL_CORE_TO_CSB_3X1) 67a3f9d6c7SDirk Eibach /* 68a3f9d6c7SDirk Eibach * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits 69a3f9d6c7SDirk Eibach * in 8308's HRCWH according to the manual, but original Freescale's 70a3f9d6c7SDirk Eibach * code has them and I've expirienced some problems using the board 71a3f9d6c7SDirk Eibach * with BDI3000 attached when I've tried to set these bits to zero 72a3f9d6c7SDirk Eibach * (UART doesn't work after the 'reset run' command). 73a3f9d6c7SDirk Eibach */ 74a3f9d6c7SDirk Eibach #define CONFIG_SYS_HRCW_HIGH (\ 75a3f9d6c7SDirk Eibach HRCWH_PCI_HOST |\ 76a3f9d6c7SDirk Eibach HRCWH_PCI1_ARBITER_ENABLE |\ 77a3f9d6c7SDirk Eibach HRCWH_CORE_ENABLE |\ 78a3f9d6c7SDirk Eibach HRCWH_FROM_0XFFF00100 |\ 79a3f9d6c7SDirk Eibach HRCWH_BOOTSEQ_DISABLE |\ 80a3f9d6c7SDirk Eibach HRCWH_SW_WATCHDOG_DISABLE |\ 81a3f9d6c7SDirk Eibach HRCWH_ROM_LOC_LOCAL_16BIT |\ 82a3f9d6c7SDirk Eibach HRCWH_RL_EXT_LEGACY |\ 83a3f9d6c7SDirk Eibach HRCWH_TSEC1M_IN_MII |\ 84a3f9d6c7SDirk Eibach HRCWH_TSEC2M_IN_RGMII |\ 85a3f9d6c7SDirk Eibach HRCWH_BIG_ENDIAN) 86a3f9d6c7SDirk Eibach 87a3f9d6c7SDirk Eibach /* 88a3f9d6c7SDirk Eibach * System IO Config 89a3f9d6c7SDirk Eibach */ 90a3f9d6c7SDirk Eibach #define CONFIG_SYS_SICRH (\ 91a3f9d6c7SDirk Eibach SICRH_ESDHC_A_SD |\ 92a3f9d6c7SDirk Eibach SICRH_ESDHC_B_SD |\ 93a3f9d6c7SDirk Eibach SICRH_ESDHC_C_SD |\ 94a3f9d6c7SDirk Eibach SICRH_GPIO_A_GPIO |\ 95a3f9d6c7SDirk Eibach SICRH_GPIO_B_GPIO |\ 96a3f9d6c7SDirk Eibach SICRH_IEEE1588_A_GPIO |\ 97a3f9d6c7SDirk Eibach SICRH_USB |\ 98a3f9d6c7SDirk Eibach SICRH_GTM_GPIO |\ 99a3f9d6c7SDirk Eibach SICRH_IEEE1588_B_GPIO |\ 100a3f9d6c7SDirk Eibach SICRH_ETSEC2_GPIO |\ 101a3f9d6c7SDirk Eibach SICRH_GPIOSEL_1 |\ 102a3f9d6c7SDirk Eibach SICRH_TMROBI_V3P3 |\ 103a3f9d6c7SDirk Eibach SICRH_TSOBI1_V2P5 |\ 104a3f9d6c7SDirk Eibach SICRH_TSOBI2_V2P5) /* 0x0037f103 */ 105a3f9d6c7SDirk Eibach #define CONFIG_SYS_SICRL (\ 106a3f9d6c7SDirk Eibach SICRL_SPI_PF0 |\ 107a3f9d6c7SDirk Eibach SICRL_UART_PF0 |\ 108a3f9d6c7SDirk Eibach SICRL_IRQ_PF0 |\ 109a3f9d6c7SDirk Eibach SICRL_I2C2_PF0 |\ 110a3f9d6c7SDirk Eibach SICRL_ETSEC1_TX_CLK) /* 0x00000000 */ 111a3f9d6c7SDirk Eibach 112a3f9d6c7SDirk Eibach /* 113a3f9d6c7SDirk Eibach * IMMR new address 114a3f9d6c7SDirk Eibach */ 115a3f9d6c7SDirk Eibach #define CONFIG_SYS_IMMR 0xE0000000 116a3f9d6c7SDirk Eibach 117a3f9d6c7SDirk Eibach /* 118a3f9d6c7SDirk Eibach * SERDES 119a3f9d6c7SDirk Eibach */ 120a3f9d6c7SDirk Eibach #define CONFIG_FSL_SERDES 121a3f9d6c7SDirk Eibach #define CONFIG_FSL_SERDES1 0xe3000 122a3f9d6c7SDirk Eibach 123a3f9d6c7SDirk Eibach /* 124a3f9d6c7SDirk Eibach * Arbiter Setup 125a3f9d6c7SDirk Eibach */ 126a3f9d6c7SDirk Eibach #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 127a3f9d6c7SDirk Eibach #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 128a3f9d6c7SDirk Eibach #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 129a3f9d6c7SDirk Eibach 130a3f9d6c7SDirk Eibach /* 131a3f9d6c7SDirk Eibach * DDR Setup 132a3f9d6c7SDirk Eibach */ 133a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 134a3f9d6c7SDirk Eibach #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 135a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 136a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 137a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 138a3f9d6c7SDirk Eibach | DDRCDR_PZ_LOZ \ 139a3f9d6c7SDirk Eibach | DDRCDR_NZ_LOZ \ 140a3f9d6c7SDirk Eibach | DDRCDR_ODT \ 141a3f9d6c7SDirk Eibach | DDRCDR_Q_DRN) 142a3f9d6c7SDirk Eibach /* 0x7b880001 */ 143a3f9d6c7SDirk Eibach /* 144a3f9d6c7SDirk Eibach * Manually set up DDR parameters 145a3f9d6c7SDirk Eibach * consist of one chip NT5TU64M16HG from NANYA 146a3f9d6c7SDirk Eibach */ 147a3f9d6c7SDirk Eibach 148a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 149a3f9d6c7SDirk Eibach 150a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 151a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 152a3f9d6c7SDirk Eibach | CSCONFIG_ODT_RD_NEVER \ 153a3f9d6c7SDirk Eibach | CSCONFIG_ODT_WR_ONLY_CURRENT \ 154a3f9d6c7SDirk Eibach | CSCONFIG_BANK_BIT_3 \ 155a3f9d6c7SDirk Eibach | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 156a3f9d6c7SDirk Eibach /* 0x80010102 */ 157a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_TIMING_3 0 158a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 159a3f9d6c7SDirk Eibach | (0 << TIMING_CFG0_WRT_SHIFT) \ 160a3f9d6c7SDirk Eibach | (0 << TIMING_CFG0_RRT_SHIFT) \ 161a3f9d6c7SDirk Eibach | (0 << TIMING_CFG0_WWT_SHIFT) \ 162a3f9d6c7SDirk Eibach | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 163a3f9d6c7SDirk Eibach | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 164a3f9d6c7SDirk Eibach | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 165a3f9d6c7SDirk Eibach | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 166a3f9d6c7SDirk Eibach /* 0x00260802 */ 167a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 168a3f9d6c7SDirk Eibach | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 169a3f9d6c7SDirk Eibach | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 170a3f9d6c7SDirk Eibach | (7 << TIMING_CFG1_CASLAT_SHIFT) \ 171a3f9d6c7SDirk Eibach | (9 << TIMING_CFG1_REFREC_SHIFT) \ 172a3f9d6c7SDirk Eibach | (2 << TIMING_CFG1_WRREC_SHIFT) \ 173a3f9d6c7SDirk Eibach | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 174a3f9d6c7SDirk Eibach | (2 << TIMING_CFG1_WRTORD_SHIFT)) 175a3f9d6c7SDirk Eibach /* 0x26279222 */ 176a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ 177a3f9d6c7SDirk Eibach | (4 << TIMING_CFG2_CPO_SHIFT) \ 178a3f9d6c7SDirk Eibach | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 179a3f9d6c7SDirk Eibach | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 180a3f9d6c7SDirk Eibach | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 181a3f9d6c7SDirk Eibach | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 182a3f9d6c7SDirk Eibach | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 183a3f9d6c7SDirk Eibach /* 0x021848c5 */ 184a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \ 185a3f9d6c7SDirk Eibach | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 186a3f9d6c7SDirk Eibach /* 0x08240100 */ 187a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 188a3f9d6c7SDirk Eibach | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 189a3f9d6c7SDirk Eibach | SDRAM_CFG_DBW_16) 190a3f9d6c7SDirk Eibach /* 0x43100000 */ 191a3f9d6c7SDirk Eibach 192a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 193a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ 194a3f9d6c7SDirk Eibach | (0x0242 << SDRAM_MODE_SD_SHIFT)) 195a3f9d6c7SDirk Eibach /* ODT 150ohm CL=4, AL=0 on SDRAM */ 196a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_MODE2 0x00000000 197a3f9d6c7SDirk Eibach 198a3f9d6c7SDirk Eibach /* 199a3f9d6c7SDirk Eibach * Memory test 200a3f9d6c7SDirk Eibach */ 201a3f9d6c7SDirk Eibach #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ 202a3f9d6c7SDirk Eibach #define CONFIG_SYS_MEMTEST_END 0x07f00000 203a3f9d6c7SDirk Eibach 204a3f9d6c7SDirk Eibach /* 205a3f9d6c7SDirk Eibach * The reserved memory 206a3f9d6c7SDirk Eibach */ 207a3f9d6c7SDirk Eibach #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 208a3f9d6c7SDirk Eibach 209a3f9d6c7SDirk Eibach #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 210a3f9d6c7SDirk Eibach #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 211a3f9d6c7SDirk Eibach 212a3f9d6c7SDirk Eibach /* 213a3f9d6c7SDirk Eibach * Initial RAM Base Address Setup 214a3f9d6c7SDirk Eibach */ 215a3f9d6c7SDirk Eibach #define CONFIG_SYS_INIT_RAM_LOCK 1 216a3f9d6c7SDirk Eibach #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 217a3f9d6c7SDirk Eibach #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 218a3f9d6c7SDirk Eibach #define CONFIG_SYS_GBL_DATA_OFFSET \ 219a3f9d6c7SDirk Eibach (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 220a3f9d6c7SDirk Eibach 221a3f9d6c7SDirk Eibach /* 222a3f9d6c7SDirk Eibach * Local Bus Configuration & Clock Setup 223a3f9d6c7SDirk Eibach */ 224a3f9d6c7SDirk Eibach #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 225a3f9d6c7SDirk Eibach #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 226a3f9d6c7SDirk Eibach #define CONFIG_SYS_LBC_LBCR 0x00040000 227a3f9d6c7SDirk Eibach 228a3f9d6c7SDirk Eibach /* 229a3f9d6c7SDirk Eibach * FLASH on the Local Bus 230a3f9d6c7SDirk Eibach */ 231a3f9d6c7SDirk Eibach #if 1 232a3f9d6c7SDirk Eibach #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 233a3f9d6c7SDirk Eibach #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 234a3f9d6c7SDirk Eibach #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 235a3f9d6c7SDirk Eibach #define CONFIG_FLASH_CFI_LEGACY 236a3f9d6c7SDirk Eibach #define CONFIG_SYS_FLASH_LEGACY_512Kx16 237a3f9d6c7SDirk Eibach #else 238a3f9d6c7SDirk Eibach #define CONFIG_SYS_NO_FLASH 239a3f9d6c7SDirk Eibach #endif 240a3f9d6c7SDirk Eibach 241a3f9d6c7SDirk Eibach #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 242a3f9d6c7SDirk Eibach #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ 243a3f9d6c7SDirk Eibach #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 244a3f9d6c7SDirk Eibach 245a3f9d6c7SDirk Eibach /* Window base at flash base */ 246a3f9d6c7SDirk Eibach #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 247a3f9d6c7SDirk Eibach #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 248a3f9d6c7SDirk Eibach 249a3f9d6c7SDirk Eibach #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 250a3f9d6c7SDirk Eibach | BR_PS_16 /* 16 bit port */ \ 251a3f9d6c7SDirk Eibach | BR_MS_GPCM /* MSEL = GPCM */ \ 252a3f9d6c7SDirk Eibach | BR_V) /* valid */ 253a3f9d6c7SDirk Eibach #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 254a3f9d6c7SDirk Eibach | OR_UPM_XAM \ 255a3f9d6c7SDirk Eibach | OR_GPCM_CSNT \ 256a3f9d6c7SDirk Eibach | OR_GPCM_ACS_DIV2 \ 257a3f9d6c7SDirk Eibach | OR_GPCM_XACS \ 258a3f9d6c7SDirk Eibach | OR_GPCM_SCY_15 \ 259a3f9d6c7SDirk Eibach | OR_GPCM_TRLX_SET \ 260a3f9d6c7SDirk Eibach | OR_GPCM_EHTR_SET) 261a3f9d6c7SDirk Eibach 262a3f9d6c7SDirk Eibach #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 263a3f9d6c7SDirk Eibach #define CONFIG_SYS_MAX_FLASH_SECT 135 264a3f9d6c7SDirk Eibach 265a3f9d6c7SDirk Eibach #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 266a3f9d6c7SDirk Eibach #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 267a3f9d6c7SDirk Eibach 268a3f9d6c7SDirk Eibach /* 269a3f9d6c7SDirk Eibach * FPGA 270a3f9d6c7SDirk Eibach */ 271a3f9d6c7SDirk Eibach #define CONFIG_SYS_FPGA0_BASE 0xE0600000 272a3f9d6c7SDirk Eibach #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ 273a3f9d6c7SDirk Eibach 274a3f9d6c7SDirk Eibach /* Window base at FPGA base */ 275a3f9d6c7SDirk Eibach #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE 276a3f9d6c7SDirk Eibach #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB) 277a3f9d6c7SDirk Eibach 278a3f9d6c7SDirk Eibach #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \ 279a3f9d6c7SDirk Eibach | BR_PS_16 /* 16 bit port */ \ 280a3f9d6c7SDirk Eibach | BR_MS_GPCM /* MSEL = GPCM */ \ 281a3f9d6c7SDirk Eibach | BR_V) /* valid */ 282*a119357cSReinhard Pfau 283a3f9d6c7SDirk Eibach #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \ 284a3f9d6c7SDirk Eibach | OR_UPM_XAM \ 285a3f9d6c7SDirk Eibach | OR_GPCM_CSNT \ 286*a119357cSReinhard Pfau | OR_GPCM_SCY_5 \ 287*a119357cSReinhard Pfau | OR_GPCM_TRLX_CLEAR \ 288*a119357cSReinhard Pfau | OR_GPCM_EHTR_CLEAR) 289a3f9d6c7SDirk Eibach 290a3f9d6c7SDirk Eibach #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE 291a3f9d6c7SDirk Eibach #define CONFIG_SYS_FPGA_DONE(k) 0x0010 292a3f9d6c7SDirk Eibach 293a3f9d6c7SDirk Eibach #define CONFIG_SYS_FPGA_COUNT 1 294a3f9d6c7SDirk Eibach 295a3f9d6c7SDirk Eibach #define CONFIG_SYS_MCLINK_MAX 3 296a3f9d6c7SDirk Eibach 297a3f9d6c7SDirk Eibach #define CONFIG_SYS_FPGA_PTR \ 298a3f9d6c7SDirk Eibach { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL } 299a3f9d6c7SDirk Eibach 300a3f9d6c7SDirk Eibach #define CONFIG_SYS_FPGA_NO_RFL_HI 301a3f9d6c7SDirk Eibach 302a3f9d6c7SDirk Eibach /* 303a3f9d6c7SDirk Eibach * Serial Port 304a3f9d6c7SDirk Eibach */ 305a3f9d6c7SDirk Eibach #define CONFIG_CONS_INDEX 2 306a3f9d6c7SDirk Eibach #define CONFIG_SYS_NS16550_SERIAL 307a3f9d6c7SDirk Eibach #define CONFIG_SYS_NS16550_REG_SIZE 1 308a3f9d6c7SDirk Eibach #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 309a3f9d6c7SDirk Eibach 310a3f9d6c7SDirk Eibach #define CONFIG_SYS_BAUDRATE_TABLE \ 311a3f9d6c7SDirk Eibach {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 312a3f9d6c7SDirk Eibach 313a3f9d6c7SDirk Eibach #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 314a3f9d6c7SDirk Eibach #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 315a3f9d6c7SDirk Eibach 316a3f9d6c7SDirk Eibach /* Use the HUSH parser */ 317a3f9d6c7SDirk Eibach #define CONFIG_SYS_HUSH_PARSER 318a3f9d6c7SDirk Eibach 319a3f9d6c7SDirk Eibach /* Pass open firmware flat tree */ 320a3f9d6c7SDirk Eibach 321a3f9d6c7SDirk Eibach /* I2C */ 322a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C 323a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_FSL 324a3f9d6c7SDirk Eibach #define CONFIG_SYS_FSL_I2C_SPEED 400000 325a3f9d6c7SDirk Eibach #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 326a3f9d6c7SDirk Eibach #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 327a3f9d6c7SDirk Eibach 328a3f9d6c7SDirk Eibach #define CONFIG_PCA953X /* NXP PCA9554 */ 32947098056SDirk Eibach #define CONFIG_CMD_PCA953X 33047098056SDirk Eibach #define CONFIG_CMD_PCA953X_INFO 33147098056SDirk Eibach #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x24, 16}, {0x25, 16}, {0x26, 16}, \ 33247098056SDirk Eibach {0x3c, 8}, {0x3d, 8}, {0x3e, 8} } 33347098056SDirk Eibach 334a3f9d6c7SDirk Eibach #define CONFIG_PCA9698 /* NXP PCA9698 */ 335a3f9d6c7SDirk Eibach 336a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS 337a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS_CH0 338a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS_SPEED_0 50000 339a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F 340a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS_CH1 341a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS_SPEED_1 50000 342a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F 343a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS_CH2 344a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS_SPEED_2 50000 345a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F 346a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS_CH3 347a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS_SPEED_3 50000 348a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F 349a3f9d6c7SDirk Eibach 350a3f9d6c7SDirk Eibach /* 351a3f9d6c7SDirk Eibach * Software (bit-bang) I2C driver configuration 352a3f9d6c7SDirk Eibach */ 353a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT 354a3f9d6c7SDirk Eibach #define CONFIG_SOFT_I2C_READ_REPEATED_START 355a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SPEED 50000 356a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F 357a3f9d6c7SDirk Eibach #define I2C_SOFT_DECLARATIONS2 358a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 359a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F 360a3f9d6c7SDirk Eibach #define I2C_SOFT_DECLARATIONS3 361a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000 362a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F 363a3f9d6c7SDirk Eibach #define I2C_SOFT_DECLARATIONS4 364a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 365a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F 366a3f9d6c7SDirk Eibach #ifdef CONFIG_STRIDER_CON 367a3f9d6c7SDirk Eibach #define I2C_SOFT_DECLARATIONS5 368a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000 369a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F 370a3f9d6c7SDirk Eibach #define I2C_SOFT_DECLARATIONS6 371a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SPEED_6 50000 372a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F 373a3f9d6c7SDirk Eibach #define I2C_SOFT_DECLARATIONS7 374a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SPEED_7 50000 375a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F 376a3f9d6c7SDirk Eibach #define I2C_SOFT_DECLARATIONS8 377a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000 378a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F 379a3f9d6c7SDirk Eibach #endif 380a3f9d6c7SDirk Eibach 381a3f9d6c7SDirk Eibach #ifdef CONFIG_STRIDER_CON 382a3f9d6c7SDirk Eibach #define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8} 383a3f9d6c7SDirk Eibach #define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8} 384a3f9d6c7SDirk Eibach #define CONFIG_SYS_ADV7611_I2C {5, 6, 7, 8} 385a3f9d6c7SDirk Eibach #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 386a3f9d6c7SDirk Eibach #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \ 387a3f9d6c7SDirk Eibach {12, 0x4c} } 388a3f9d6c7SDirk Eibach #else 389a3f9d6c7SDirk Eibach #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4} 390a3f9d6c7SDirk Eibach #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4} 391a3f9d6c7SDirk Eibach #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 392a3f9d6c7SDirk Eibach #define CONFIG_STRIDER_FANS { {2, 0x18}, {3, 0x18}, \ 393a3f9d6c7SDirk Eibach {4, 0x18} } 394a3f9d6c7SDirk Eibach #endif 395a3f9d6c7SDirk Eibach 396a3f9d6c7SDirk Eibach #ifndef __ASSEMBLY__ 397a3f9d6c7SDirk Eibach void fpga_gpio_set(unsigned int bus, int pin); 398a3f9d6c7SDirk Eibach void fpga_gpio_clear(unsigned int bus, int pin); 399a3f9d6c7SDirk Eibach int fpga_gpio_get(unsigned int bus, int pin); 400a3f9d6c7SDirk Eibach #endif 401a3f9d6c7SDirk Eibach 402a3f9d6c7SDirk Eibach #ifdef CONFIG_STRIDER_CON 403a3f9d6c7SDirk Eibach #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040) 404a3f9d6c7SDirk Eibach #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020) 405a3f9d6c7SDirk Eibach #define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \ 406a3f9d6c7SDirk Eibach (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR) 407a3f9d6c7SDirk Eibach #else 408a3f9d6c7SDirk Eibach #define I2C_SDA_GPIO 0x0040 409a3f9d6c7SDirk Eibach #define I2C_SCL_GPIO 0x0020 410a3f9d6c7SDirk Eibach #define I2C_FPGA_IDX I2C_ADAP_HWNR 411a3f9d6c7SDirk Eibach #endif 412a3f9d6c7SDirk Eibach #define I2C_ACTIVE { } 413a3f9d6c7SDirk Eibach #define I2C_TRISTATE { } 414a3f9d6c7SDirk Eibach #define I2C_READ \ 415a3f9d6c7SDirk Eibach (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0) 416a3f9d6c7SDirk Eibach #define I2C_SDA(bit) \ 417a3f9d6c7SDirk Eibach do { \ 418a3f9d6c7SDirk Eibach if (bit) \ 419a3f9d6c7SDirk Eibach fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \ 420a3f9d6c7SDirk Eibach else \ 421a3f9d6c7SDirk Eibach fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \ 422a3f9d6c7SDirk Eibach } while (0) 423a3f9d6c7SDirk Eibach #define I2C_SCL(bit) \ 424a3f9d6c7SDirk Eibach do { \ 425a3f9d6c7SDirk Eibach if (bit) \ 426a3f9d6c7SDirk Eibach fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \ 427a3f9d6c7SDirk Eibach else \ 428a3f9d6c7SDirk Eibach fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \ 429a3f9d6c7SDirk Eibach } while (0) 430a3f9d6c7SDirk Eibach #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ 431a3f9d6c7SDirk Eibach 432a3f9d6c7SDirk Eibach /* 433a3f9d6c7SDirk Eibach * Software (bit-bang) MII driver configuration 434a3f9d6c7SDirk Eibach */ 435a3f9d6c7SDirk Eibach #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 436a3f9d6c7SDirk Eibach #define CONFIG_BITBANGMII_MULTI 437a3f9d6c7SDirk Eibach 438a3f9d6c7SDirk Eibach /* 439a3f9d6c7SDirk Eibach * OSD Setup 440a3f9d6c7SDirk Eibach */ 441a3f9d6c7SDirk Eibach #define CONFIG_SYS_OSD_SCREENS 1 442a3f9d6c7SDirk Eibach #define CONFIG_SYS_DP501_DIFFERENTIAL 443a3f9d6c7SDirk Eibach #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ 444a3f9d6c7SDirk Eibach 445a3f9d6c7SDirk Eibach /* 446a3f9d6c7SDirk Eibach * General PCI 447a3f9d6c7SDirk Eibach * Addresses are mapped 1-1. 448a3f9d6c7SDirk Eibach */ 449a3f9d6c7SDirk Eibach #define CONFIG_SYS_PCIE1_BASE 0xA0000000 450a3f9d6c7SDirk Eibach #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 451a3f9d6c7SDirk Eibach #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 452a3f9d6c7SDirk Eibach #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 453a3f9d6c7SDirk Eibach #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 454a3f9d6c7SDirk Eibach #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 455a3f9d6c7SDirk Eibach #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 456a3f9d6c7SDirk Eibach #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 457a3f9d6c7SDirk Eibach #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 458a3f9d6c7SDirk Eibach 459a3f9d6c7SDirk Eibach /* enable PCIE clock */ 460a3f9d6c7SDirk Eibach #define CONFIG_SYS_SCCR_PCIEXP1CM 1 461a3f9d6c7SDirk Eibach 462a3f9d6c7SDirk Eibach #define CONFIG_PCI 463a3f9d6c7SDirk Eibach #define CONFIG_PCI_INDIRECT_BRIDGE 464a3f9d6c7SDirk Eibach #define CONFIG_PCIE 465a3f9d6c7SDirk Eibach 466a3f9d6c7SDirk Eibach #define CONFIG_PCI_PNP /* do pci plug-and-play */ 467a3f9d6c7SDirk Eibach 468a3f9d6c7SDirk Eibach #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 469a3f9d6c7SDirk Eibach #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 470a3f9d6c7SDirk Eibach 471a3f9d6c7SDirk Eibach /* 472a3f9d6c7SDirk Eibach * TSEC 473a3f9d6c7SDirk Eibach */ 474a3f9d6c7SDirk Eibach #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 475a3f9d6c7SDirk Eibach #define CONFIG_SYS_TSEC1_OFFSET 0x24000 476a3f9d6c7SDirk Eibach #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 477a3f9d6c7SDirk Eibach 478a3f9d6c7SDirk Eibach /* 479a3f9d6c7SDirk Eibach * TSEC ethernet configuration 480a3f9d6c7SDirk Eibach */ 481a3f9d6c7SDirk Eibach #define CONFIG_MII 1 /* MII PHY management */ 482a3f9d6c7SDirk Eibach #define CONFIG_TSEC1 483a3f9d6c7SDirk Eibach #define CONFIG_TSEC1_NAME "eTSEC0" 484a3f9d6c7SDirk Eibach #define TSEC1_PHY_ADDR 1 485a3f9d6c7SDirk Eibach #define TSEC1_PHYIDX 0 486a3f9d6c7SDirk Eibach #define TSEC1_FLAGS 0 487a3f9d6c7SDirk Eibach 488a3f9d6c7SDirk Eibach /* Options are: eTSEC[0-1] */ 489a3f9d6c7SDirk Eibach #define CONFIG_ETHPRIME "eTSEC0" 490a3f9d6c7SDirk Eibach 491a3f9d6c7SDirk Eibach /* 492a3f9d6c7SDirk Eibach * Environment 493a3f9d6c7SDirk Eibach */ 494a3f9d6c7SDirk Eibach #if 1 495a3f9d6c7SDirk Eibach #define CONFIG_ENV_IS_IN_FLASH 1 496a3f9d6c7SDirk Eibach #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 497a3f9d6c7SDirk Eibach CONFIG_SYS_MONITOR_LEN) 498a3f9d6c7SDirk Eibach #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 499a3f9d6c7SDirk Eibach #define CONFIG_ENV_SIZE 0x2000 500a3f9d6c7SDirk Eibach #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 501a3f9d6c7SDirk Eibach #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 502a3f9d6c7SDirk Eibach #else 503a3f9d6c7SDirk Eibach #define CONFIG_ENV_IS_NOWHERE 504a3f9d6c7SDirk Eibach #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 505a3f9d6c7SDirk Eibach #endif 506a3f9d6c7SDirk Eibach 507a3f9d6c7SDirk Eibach #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 508a3f9d6c7SDirk Eibach #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 509a3f9d6c7SDirk Eibach 510a3f9d6c7SDirk Eibach /* 511a3f9d6c7SDirk Eibach * Command line configuration. 512a3f9d6c7SDirk Eibach */ 513a3f9d6c7SDirk Eibach #define CONFIG_CMD_I2C 514a3f9d6c7SDirk Eibach #define CONFIG_CMD_MII 515a3f9d6c7SDirk Eibach #define CONFIG_CMD_PCI 516a3f9d6c7SDirk Eibach #define CONFIG_CMD_PING 517a3f9d6c7SDirk Eibach 518a3f9d6c7SDirk Eibach #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 519a3f9d6c7SDirk Eibach #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 520a3f9d6c7SDirk Eibach 521a3f9d6c7SDirk Eibach /* 522a3f9d6c7SDirk Eibach * Miscellaneous configurable options 523a3f9d6c7SDirk Eibach */ 524a3f9d6c7SDirk Eibach #define CONFIG_SYS_LONGHELP /* undef to save memory */ 525a3f9d6c7SDirk Eibach #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 526a3f9d6c7SDirk Eibach #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 527a3f9d6c7SDirk Eibach 528a3f9d6c7SDirk Eibach #undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ 529a3f9d6c7SDirk Eibach 530a3f9d6c7SDirk Eibach #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 531a3f9d6c7SDirk Eibach 532a3f9d6c7SDirk Eibach #define CONFIG_SYS_CONSOLE_INFO_QUIET 533a3f9d6c7SDirk Eibach 534a3f9d6c7SDirk Eibach /* Print Buffer Size */ 535a3f9d6c7SDirk Eibach #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 536a3f9d6c7SDirk Eibach #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 537a3f9d6c7SDirk Eibach #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 538a3f9d6c7SDirk Eibach 539a3f9d6c7SDirk Eibach /* 540a3f9d6c7SDirk Eibach * For booting Linux, the board info and command line data 541a3f9d6c7SDirk Eibach * have to be in the first 256 MB of memory, since this is 542a3f9d6c7SDirk Eibach * the maximum mapped by the Linux kernel during initialization. 543a3f9d6c7SDirk Eibach */ 544a3f9d6c7SDirk Eibach #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 545a3f9d6c7SDirk Eibach 546a3f9d6c7SDirk Eibach /* 547a3f9d6c7SDirk Eibach * Core HID Setup 548a3f9d6c7SDirk Eibach */ 549a3f9d6c7SDirk Eibach #define CONFIG_SYS_HID0_INIT 0x000000000 550a3f9d6c7SDirk Eibach #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 551a3f9d6c7SDirk Eibach HID0_ENABLE_INSTRUCTION_CACHE | \ 552a3f9d6c7SDirk Eibach HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 553a3f9d6c7SDirk Eibach #define CONFIG_SYS_HID2 HID2_HBE 554a3f9d6c7SDirk Eibach 555a3f9d6c7SDirk Eibach /* 556a3f9d6c7SDirk Eibach * MMU Setup 557a3f9d6c7SDirk Eibach */ 558a3f9d6c7SDirk Eibach 559a3f9d6c7SDirk Eibach /* DDR: cache cacheable */ 560a3f9d6c7SDirk Eibach #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 561a3f9d6c7SDirk Eibach BATL_MEMCOHERENCE) 562a3f9d6c7SDirk Eibach #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ 563a3f9d6c7SDirk Eibach BATU_VS | BATU_VP) 564a3f9d6c7SDirk Eibach #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 565a3f9d6c7SDirk Eibach #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 566a3f9d6c7SDirk Eibach 567a3f9d6c7SDirk Eibach /* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */ 568a3f9d6c7SDirk Eibach #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 569a3f9d6c7SDirk Eibach BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 570a3f9d6c7SDirk Eibach #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ 571a3f9d6c7SDirk Eibach BATU_VP) 572a3f9d6c7SDirk Eibach #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 573a3f9d6c7SDirk Eibach #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 574a3f9d6c7SDirk Eibach 575a3f9d6c7SDirk Eibach /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 576a3f9d6c7SDirk Eibach #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 577a3f9d6c7SDirk Eibach BATL_MEMCOHERENCE) 578a3f9d6c7SDirk Eibach #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ 579a3f9d6c7SDirk Eibach BATU_VS | BATU_VP) 580a3f9d6c7SDirk Eibach #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 581a3f9d6c7SDirk Eibach BATL_CACHEINHIBIT | \ 582a3f9d6c7SDirk Eibach BATL_GUARDEDSTORAGE) 583a3f9d6c7SDirk Eibach #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 584a3f9d6c7SDirk Eibach 585a3f9d6c7SDirk Eibach /* Stack in dcache: cacheable, no memory coherence */ 586a3f9d6c7SDirk Eibach #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 587a3f9d6c7SDirk Eibach #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 588a3f9d6c7SDirk Eibach BATU_VS | BATU_VP) 589a3f9d6c7SDirk Eibach #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 590a3f9d6c7SDirk Eibach #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 591a3f9d6c7SDirk Eibach 592a3f9d6c7SDirk Eibach /* 593a3f9d6c7SDirk Eibach * Environment Configuration 594a3f9d6c7SDirk Eibach */ 595a3f9d6c7SDirk Eibach 596a3f9d6c7SDirk Eibach #define CONFIG_ENV_OVERWRITE 597a3f9d6c7SDirk Eibach 598a3f9d6c7SDirk Eibach #if defined(CONFIG_TSEC_ENET) 599a3f9d6c7SDirk Eibach #define CONFIG_HAS_ETH0 600a3f9d6c7SDirk Eibach #endif 601a3f9d6c7SDirk Eibach 602a3f9d6c7SDirk Eibach #define CONFIG_BAUDRATE 115200 603a3f9d6c7SDirk Eibach 604a3f9d6c7SDirk Eibach #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 605a3f9d6c7SDirk Eibach 606a3f9d6c7SDirk Eibach #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ 607a3f9d6c7SDirk Eibach 608a3f9d6c7SDirk Eibach #define CONFIG_HOSTNAME hrcon 609a3f9d6c7SDirk Eibach #define CONFIG_ROOTPATH "/opt/nfsroot" 610a3f9d6c7SDirk Eibach #define CONFIG_BOOTFILE "uImage" 611a3f9d6c7SDirk Eibach 612a3f9d6c7SDirk Eibach #define CONFIG_PREBOOT /* enable preboot variable */ 613a3f9d6c7SDirk Eibach 614a3f9d6c7SDirk Eibach #define CONFIG_EXTRA_ENV_SETTINGS \ 615a3f9d6c7SDirk Eibach "netdev=eth0\0" \ 616a3f9d6c7SDirk Eibach "consoledev=ttyS1\0" \ 617a3f9d6c7SDirk Eibach "u-boot=u-boot.bin\0" \ 618a3f9d6c7SDirk Eibach "kernel_addr=1000000\0" \ 619a3f9d6c7SDirk Eibach "fdt_addr=C00000\0" \ 620a3f9d6c7SDirk Eibach "fdtfile=hrcon.dtb\0" \ 621a3f9d6c7SDirk Eibach "load=tftp ${loadaddr} ${u-boot}\0" \ 622a3f9d6c7SDirk Eibach "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 623a3f9d6c7SDirk Eibach " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ 624a3f9d6c7SDirk Eibach " +${filesize};cp.b ${fileaddr} " \ 625a3f9d6c7SDirk Eibach __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 626a3f9d6c7SDirk Eibach "upd=run load update\0" \ 627a3f9d6c7SDirk Eibach 628a3f9d6c7SDirk Eibach #define CONFIG_NFSBOOTCOMMAND \ 629a3f9d6c7SDirk Eibach "setenv bootargs root=/dev/nfs rw " \ 630a3f9d6c7SDirk Eibach "nfsroot=$serverip:$rootpath " \ 631a3f9d6c7SDirk Eibach "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 632a3f9d6c7SDirk Eibach "console=$consoledev,$baudrate $othbootargs;" \ 633a3f9d6c7SDirk Eibach "tftp ${kernel_addr} $bootfile;" \ 634a3f9d6c7SDirk Eibach "tftp ${fdt_addr} $fdtfile;" \ 635a3f9d6c7SDirk Eibach "bootm ${kernel_addr} - ${fdt_addr}" 636a3f9d6c7SDirk Eibach 637a3f9d6c7SDirk Eibach #define CONFIG_MMCBOOTCOMMAND \ 638a3f9d6c7SDirk Eibach "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ 639a3f9d6c7SDirk Eibach "console=$consoledev,$baudrate $othbootargs;" \ 640a3f9d6c7SDirk Eibach "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \ 641a3f9d6c7SDirk Eibach "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \ 642a3f9d6c7SDirk Eibach "bootm ${kernel_addr} - ${fdt_addr}" 643a3f9d6c7SDirk Eibach 644a3f9d6c7SDirk Eibach #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND 645a3f9d6c7SDirk Eibach 646a3f9d6c7SDirk Eibach 647a3f9d6c7SDirk Eibach #endif /* __CONFIG_H */ 648