1a3f9d6c7SDirk Eibach /* 2a3f9d6c7SDirk Eibach * (C) Copyright 2014 3d38826a3SMario Six * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc 4a3f9d6c7SDirk Eibach * 5a3f9d6c7SDirk Eibach * 6a3f9d6c7SDirk Eibach * SPDX-License-Identifier: GPL-2.0+ 7a3f9d6c7SDirk Eibach */ 8a3f9d6c7SDirk Eibach 9a3f9d6c7SDirk Eibach #ifndef __CONFIG_H 10a3f9d6c7SDirk Eibach #define __CONFIG_H 11a3f9d6c7SDirk Eibach 12a3f9d6c7SDirk Eibach /* 13a3f9d6c7SDirk Eibach * High Level Configuration Options 14a3f9d6c7SDirk Eibach */ 15a3f9d6c7SDirk Eibach #define CONFIG_E300 1 /* E300 family */ 16a3f9d6c7SDirk Eibach #define CONFIG_MPC83xx 1 /* MPC83xx family */ 17a3f9d6c7SDirk Eibach #define CONFIG_MPC830x 1 /* MPC830x family */ 18a3f9d6c7SDirk Eibach #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ 19a3f9d6c7SDirk Eibach #define CONFIG_STRIDER 1 /* STRIDER board specific */ 20a3f9d6c7SDirk Eibach 21a3f9d6c7SDirk Eibach #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 22a3f9d6c7SDirk Eibach 23a3f9d6c7SDirk Eibach /* 24a3f9d6c7SDirk Eibach * System Clock Setup 25a3f9d6c7SDirk Eibach */ 26a3f9d6c7SDirk Eibach #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ 27a3f9d6c7SDirk Eibach #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 28a3f9d6c7SDirk Eibach 29a3f9d6c7SDirk Eibach /* 30a3f9d6c7SDirk Eibach * Hardware Reset Configuration Word 31a3f9d6c7SDirk Eibach * if CLKIN is 66.66MHz, then 32a3f9d6c7SDirk Eibach * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz 33a3f9d6c7SDirk Eibach * We choose the A type silicon as default, so the core is 400Mhz. 34a3f9d6c7SDirk Eibach */ 35a3f9d6c7SDirk Eibach #define CONFIG_SYS_HRCW_LOW (\ 36a3f9d6c7SDirk Eibach HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 37a3f9d6c7SDirk Eibach HRCWL_DDR_TO_SCB_CLK_2X1 |\ 38a3f9d6c7SDirk Eibach HRCWL_SVCOD_DIV_2 |\ 39a3f9d6c7SDirk Eibach HRCWL_CSB_TO_CLKIN_4X1 |\ 40a3f9d6c7SDirk Eibach HRCWL_CORE_TO_CSB_3X1) 41a3f9d6c7SDirk Eibach /* 42a3f9d6c7SDirk Eibach * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits 43a3f9d6c7SDirk Eibach * in 8308's HRCWH according to the manual, but original Freescale's 44a3f9d6c7SDirk Eibach * code has them and I've expirienced some problems using the board 45a3f9d6c7SDirk Eibach * with BDI3000 attached when I've tried to set these bits to zero 46a3f9d6c7SDirk Eibach * (UART doesn't work after the 'reset run' command). 47a3f9d6c7SDirk Eibach */ 48a3f9d6c7SDirk Eibach #define CONFIG_SYS_HRCW_HIGH (\ 49a3f9d6c7SDirk Eibach HRCWH_PCI_HOST |\ 50a3f9d6c7SDirk Eibach HRCWH_PCI1_ARBITER_ENABLE |\ 51a3f9d6c7SDirk Eibach HRCWH_CORE_ENABLE |\ 52a3f9d6c7SDirk Eibach HRCWH_FROM_0XFFF00100 |\ 53a3f9d6c7SDirk Eibach HRCWH_BOOTSEQ_DISABLE |\ 54a3f9d6c7SDirk Eibach HRCWH_SW_WATCHDOG_DISABLE |\ 55a3f9d6c7SDirk Eibach HRCWH_ROM_LOC_LOCAL_16BIT |\ 56a3f9d6c7SDirk Eibach HRCWH_RL_EXT_LEGACY |\ 57a3f9d6c7SDirk Eibach HRCWH_TSEC1M_IN_MII |\ 58a3f9d6c7SDirk Eibach HRCWH_TSEC2M_IN_RGMII |\ 59a3f9d6c7SDirk Eibach HRCWH_BIG_ENDIAN) 60a3f9d6c7SDirk Eibach 61a3f9d6c7SDirk Eibach /* 62a3f9d6c7SDirk Eibach * System IO Config 63a3f9d6c7SDirk Eibach */ 64a3f9d6c7SDirk Eibach #define CONFIG_SYS_SICRH (\ 65a3f9d6c7SDirk Eibach SICRH_ESDHC_A_SD |\ 66a3f9d6c7SDirk Eibach SICRH_ESDHC_B_SD |\ 67a3f9d6c7SDirk Eibach SICRH_ESDHC_C_SD |\ 68a3f9d6c7SDirk Eibach SICRH_GPIO_A_GPIO |\ 69a3f9d6c7SDirk Eibach SICRH_GPIO_B_GPIO |\ 70a3f9d6c7SDirk Eibach SICRH_IEEE1588_A_GPIO |\ 71a3f9d6c7SDirk Eibach SICRH_USB |\ 72a3f9d6c7SDirk Eibach SICRH_GTM_GPIO |\ 73a3f9d6c7SDirk Eibach SICRH_IEEE1588_B_GPIO |\ 74a3f9d6c7SDirk Eibach SICRH_ETSEC2_GPIO |\ 75a3f9d6c7SDirk Eibach SICRH_GPIOSEL_1 |\ 76a3f9d6c7SDirk Eibach SICRH_TMROBI_V3P3 |\ 77a3f9d6c7SDirk Eibach SICRH_TSOBI1_V2P5 |\ 78a3f9d6c7SDirk Eibach SICRH_TSOBI2_V2P5) /* 0x0037f103 */ 79a3f9d6c7SDirk Eibach #define CONFIG_SYS_SICRL (\ 80a3f9d6c7SDirk Eibach SICRL_SPI_PF0 |\ 81a3f9d6c7SDirk Eibach SICRL_UART_PF0 |\ 82a3f9d6c7SDirk Eibach SICRL_IRQ_PF0 |\ 83a3f9d6c7SDirk Eibach SICRL_I2C2_PF0 |\ 84a3f9d6c7SDirk Eibach SICRL_ETSEC1_TX_CLK) /* 0x00000000 */ 85a3f9d6c7SDirk Eibach 86a3f9d6c7SDirk Eibach /* 87a3f9d6c7SDirk Eibach * IMMR new address 88a3f9d6c7SDirk Eibach */ 89a3f9d6c7SDirk Eibach #define CONFIG_SYS_IMMR 0xE0000000 90a3f9d6c7SDirk Eibach 91a3f9d6c7SDirk Eibach /* 92a3f9d6c7SDirk Eibach * SERDES 93a3f9d6c7SDirk Eibach */ 94a3f9d6c7SDirk Eibach #define CONFIG_FSL_SERDES 95a3f9d6c7SDirk Eibach #define CONFIG_FSL_SERDES1 0xe3000 96a3f9d6c7SDirk Eibach 97a3f9d6c7SDirk Eibach /* 98a3f9d6c7SDirk Eibach * Arbiter Setup 99a3f9d6c7SDirk Eibach */ 100a3f9d6c7SDirk Eibach #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ 101a3f9d6c7SDirk Eibach #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ 102a3f9d6c7SDirk Eibach #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ 103a3f9d6c7SDirk Eibach 104a3f9d6c7SDirk Eibach /* 105a3f9d6c7SDirk Eibach * DDR Setup 106a3f9d6c7SDirk Eibach */ 107a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ 108a3f9d6c7SDirk Eibach #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 109a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 110a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 111a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 112a3f9d6c7SDirk Eibach | DDRCDR_PZ_LOZ \ 113a3f9d6c7SDirk Eibach | DDRCDR_NZ_LOZ \ 114a3f9d6c7SDirk Eibach | DDRCDR_ODT \ 115a3f9d6c7SDirk Eibach | DDRCDR_Q_DRN) 116a3f9d6c7SDirk Eibach /* 0x7b880001 */ 117a3f9d6c7SDirk Eibach /* 118a3f9d6c7SDirk Eibach * Manually set up DDR parameters 119a3f9d6c7SDirk Eibach * consist of one chip NT5TU64M16HG from NANYA 120a3f9d6c7SDirk Eibach */ 121a3f9d6c7SDirk Eibach 122a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 123a3f9d6c7SDirk Eibach 124a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 125a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 126a3f9d6c7SDirk Eibach | CSCONFIG_ODT_RD_NEVER \ 127a3f9d6c7SDirk Eibach | CSCONFIG_ODT_WR_ONLY_CURRENT \ 128a3f9d6c7SDirk Eibach | CSCONFIG_BANK_BIT_3 \ 129a3f9d6c7SDirk Eibach | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 130a3f9d6c7SDirk Eibach /* 0x80010102 */ 131a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_TIMING_3 0 132a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 133a3f9d6c7SDirk Eibach | (0 << TIMING_CFG0_WRT_SHIFT) \ 134a3f9d6c7SDirk Eibach | (0 << TIMING_CFG0_RRT_SHIFT) \ 135a3f9d6c7SDirk Eibach | (0 << TIMING_CFG0_WWT_SHIFT) \ 136a3f9d6c7SDirk Eibach | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 137a3f9d6c7SDirk Eibach | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 138a3f9d6c7SDirk Eibach | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 139a3f9d6c7SDirk Eibach | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 140a3f9d6c7SDirk Eibach /* 0x00260802 */ 141a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 142a3f9d6c7SDirk Eibach | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 143a3f9d6c7SDirk Eibach | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 144a3f9d6c7SDirk Eibach | (7 << TIMING_CFG1_CASLAT_SHIFT) \ 145a3f9d6c7SDirk Eibach | (9 << TIMING_CFG1_REFREC_SHIFT) \ 146a3f9d6c7SDirk Eibach | (2 << TIMING_CFG1_WRREC_SHIFT) \ 147a3f9d6c7SDirk Eibach | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 148a3f9d6c7SDirk Eibach | (2 << TIMING_CFG1_WRTORD_SHIFT)) 149a3f9d6c7SDirk Eibach /* 0x26279222 */ 150a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ 151a3f9d6c7SDirk Eibach | (4 << TIMING_CFG2_CPO_SHIFT) \ 152a3f9d6c7SDirk Eibach | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 153a3f9d6c7SDirk Eibach | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 154a3f9d6c7SDirk Eibach | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 155a3f9d6c7SDirk Eibach | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 156a3f9d6c7SDirk Eibach | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 157a3f9d6c7SDirk Eibach /* 0x021848c5 */ 158a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \ 159a3f9d6c7SDirk Eibach | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 160a3f9d6c7SDirk Eibach /* 0x08240100 */ 161a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 162a3f9d6c7SDirk Eibach | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 163a3f9d6c7SDirk Eibach | SDRAM_CFG_DBW_16) 164a3f9d6c7SDirk Eibach /* 0x43100000 */ 165a3f9d6c7SDirk Eibach 166a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 167a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ 168a3f9d6c7SDirk Eibach | (0x0242 << SDRAM_MODE_SD_SHIFT)) 169a3f9d6c7SDirk Eibach /* ODT 150ohm CL=4, AL=0 on SDRAM */ 170a3f9d6c7SDirk Eibach #define CONFIG_SYS_DDR_MODE2 0x00000000 171a3f9d6c7SDirk Eibach 172a3f9d6c7SDirk Eibach /* 173a3f9d6c7SDirk Eibach * Memory test 174a3f9d6c7SDirk Eibach */ 175a3f9d6c7SDirk Eibach #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ 176a3f9d6c7SDirk Eibach #define CONFIG_SYS_MEMTEST_END 0x07f00000 177a3f9d6c7SDirk Eibach 178a3f9d6c7SDirk Eibach /* 179a3f9d6c7SDirk Eibach * The reserved memory 180a3f9d6c7SDirk Eibach */ 181a3f9d6c7SDirk Eibach #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 182a3f9d6c7SDirk Eibach 183a3f9d6c7SDirk Eibach #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 184a3f9d6c7SDirk Eibach #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 185a3f9d6c7SDirk Eibach 186a3f9d6c7SDirk Eibach /* 187a3f9d6c7SDirk Eibach * Initial RAM Base Address Setup 188a3f9d6c7SDirk Eibach */ 189a3f9d6c7SDirk Eibach #define CONFIG_SYS_INIT_RAM_LOCK 1 190a3f9d6c7SDirk Eibach #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 191a3f9d6c7SDirk Eibach #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 192a3f9d6c7SDirk Eibach #define CONFIG_SYS_GBL_DATA_OFFSET \ 193a3f9d6c7SDirk Eibach (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 194a3f9d6c7SDirk Eibach 195a3f9d6c7SDirk Eibach /* 196a3f9d6c7SDirk Eibach * Local Bus Configuration & Clock Setup 197a3f9d6c7SDirk Eibach */ 198a3f9d6c7SDirk Eibach #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP 199a3f9d6c7SDirk Eibach #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 200a3f9d6c7SDirk Eibach #define CONFIG_SYS_LBC_LBCR 0x00040000 201a3f9d6c7SDirk Eibach 202a3f9d6c7SDirk Eibach /* 203a3f9d6c7SDirk Eibach * FLASH on the Local Bus 204a3f9d6c7SDirk Eibach */ 205a3f9d6c7SDirk Eibach #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 206a3f9d6c7SDirk Eibach #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 207a3f9d6c7SDirk Eibach #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 208a3f9d6c7SDirk Eibach #define CONFIG_FLASH_CFI_LEGACY 209a3f9d6c7SDirk Eibach #define CONFIG_SYS_FLASH_LEGACY_512Kx16 210a3f9d6c7SDirk Eibach 211a3f9d6c7SDirk Eibach #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 212a3f9d6c7SDirk Eibach #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ 213a3f9d6c7SDirk Eibach #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ 214a3f9d6c7SDirk Eibach 215a3f9d6c7SDirk Eibach /* Window base at flash base */ 216a3f9d6c7SDirk Eibach #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 217a3f9d6c7SDirk Eibach #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) 218a3f9d6c7SDirk Eibach 219a3f9d6c7SDirk Eibach #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ 220a3f9d6c7SDirk Eibach | BR_PS_16 /* 16 bit port */ \ 221a3f9d6c7SDirk Eibach | BR_MS_GPCM /* MSEL = GPCM */ \ 222a3f9d6c7SDirk Eibach | BR_V) /* valid */ 223a3f9d6c7SDirk Eibach #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 224a3f9d6c7SDirk Eibach | OR_UPM_XAM \ 225a3f9d6c7SDirk Eibach | OR_GPCM_CSNT \ 226a3f9d6c7SDirk Eibach | OR_GPCM_ACS_DIV2 \ 227a3f9d6c7SDirk Eibach | OR_GPCM_XACS \ 228a3f9d6c7SDirk Eibach | OR_GPCM_SCY_15 \ 229a3f9d6c7SDirk Eibach | OR_GPCM_TRLX_SET \ 230a3f9d6c7SDirk Eibach | OR_GPCM_EHTR_SET) 231a3f9d6c7SDirk Eibach 232a3f9d6c7SDirk Eibach #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 233a3f9d6c7SDirk Eibach #define CONFIG_SYS_MAX_FLASH_SECT 135 234a3f9d6c7SDirk Eibach 235a3f9d6c7SDirk Eibach #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 236a3f9d6c7SDirk Eibach #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 237a3f9d6c7SDirk Eibach 238a3f9d6c7SDirk Eibach /* 239a3f9d6c7SDirk Eibach * FPGA 240a3f9d6c7SDirk Eibach */ 241a3f9d6c7SDirk Eibach #define CONFIG_SYS_FPGA0_BASE 0xE0600000 242a3f9d6c7SDirk Eibach #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ 243a3f9d6c7SDirk Eibach 244a3f9d6c7SDirk Eibach /* Window base at FPGA base */ 245a3f9d6c7SDirk Eibach #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE 246a3f9d6c7SDirk Eibach #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB) 247a3f9d6c7SDirk Eibach 248a3f9d6c7SDirk Eibach #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \ 249a3f9d6c7SDirk Eibach | BR_PS_16 /* 16 bit port */ \ 250a3f9d6c7SDirk Eibach | BR_MS_GPCM /* MSEL = GPCM */ \ 251a3f9d6c7SDirk Eibach | BR_V) /* valid */ 252a119357cSReinhard Pfau 253a3f9d6c7SDirk Eibach #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \ 254a3f9d6c7SDirk Eibach | OR_UPM_XAM \ 255a3f9d6c7SDirk Eibach | OR_GPCM_CSNT \ 256a119357cSReinhard Pfau | OR_GPCM_SCY_5 \ 257a119357cSReinhard Pfau | OR_GPCM_TRLX_CLEAR \ 258a119357cSReinhard Pfau | OR_GPCM_EHTR_CLEAR) 259a3f9d6c7SDirk Eibach 260a3f9d6c7SDirk Eibach #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE 261a3f9d6c7SDirk Eibach #define CONFIG_SYS_FPGA_DONE(k) 0x0010 262a3f9d6c7SDirk Eibach 263a3f9d6c7SDirk Eibach #define CONFIG_SYS_FPGA_COUNT 1 264a3f9d6c7SDirk Eibach 265a3f9d6c7SDirk Eibach #define CONFIG_SYS_MCLINK_MAX 3 266a3f9d6c7SDirk Eibach 267a3f9d6c7SDirk Eibach #define CONFIG_SYS_FPGA_PTR \ 268a3f9d6c7SDirk Eibach { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL } 269a3f9d6c7SDirk Eibach 270a3f9d6c7SDirk Eibach #define CONFIG_SYS_FPGA_NO_RFL_HI 271a3f9d6c7SDirk Eibach 272a3f9d6c7SDirk Eibach /* 273a3f9d6c7SDirk Eibach * Serial Port 274a3f9d6c7SDirk Eibach */ 275a3f9d6c7SDirk Eibach #define CONFIG_SYS_NS16550_SERIAL 276a3f9d6c7SDirk Eibach #define CONFIG_SYS_NS16550_REG_SIZE 1 277a3f9d6c7SDirk Eibach #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 278a3f9d6c7SDirk Eibach 279a3f9d6c7SDirk Eibach #define CONFIG_SYS_BAUDRATE_TABLE \ 280a3f9d6c7SDirk Eibach {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 281a3f9d6c7SDirk Eibach 282a3f9d6c7SDirk Eibach #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 283a3f9d6c7SDirk Eibach #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 284a3f9d6c7SDirk Eibach 285a3f9d6c7SDirk Eibach /* Pass open firmware flat tree */ 286a3f9d6c7SDirk Eibach 287a3f9d6c7SDirk Eibach /* I2C */ 288a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C 289a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_FSL 290a3f9d6c7SDirk Eibach #define CONFIG_SYS_FSL_I2C_SPEED 400000 291a3f9d6c7SDirk Eibach #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 292a3f9d6c7SDirk Eibach #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 293a3f9d6c7SDirk Eibach 294a3f9d6c7SDirk Eibach #define CONFIG_PCA953X /* NXP PCA9554 */ 29547098056SDirk Eibach #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x24, 16}, {0x25, 16}, {0x26, 16}, \ 29647098056SDirk Eibach {0x3c, 8}, {0x3d, 8}, {0x3e, 8} } 29747098056SDirk Eibach 298a3f9d6c7SDirk Eibach #define CONFIG_PCA9698 /* NXP PCA9698 */ 299a3f9d6c7SDirk Eibach 300a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS 301a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS_CH0 302a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS_SPEED_0 50000 303a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F 304a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS_CH1 305a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS_SPEED_1 50000 306a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F 307a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS_CH2 308a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS_SPEED_2 50000 309a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F 310a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS_CH3 311a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS_SPEED_3 50000 312a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F 313a3f9d6c7SDirk Eibach 3141d2541baSDirk Eibach #ifdef CONFIG_STRIDER_CON_DP 3151d2541baSDirk Eibach #define CONFIG_SYS_I2C_IHS_DUAL 3161d2541baSDirk Eibach #define CONFIG_SYS_I2C_IHS_CH0_1 3171d2541baSDirk Eibach #define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000 3181d2541baSDirk Eibach #define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F 3191d2541baSDirk Eibach #define CONFIG_SYS_I2C_IHS_CH1_1 3201d2541baSDirk Eibach #define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000 3211d2541baSDirk Eibach #define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F 3221d2541baSDirk Eibach #define CONFIG_SYS_I2C_IHS_CH2_1 3231d2541baSDirk Eibach #define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000 3241d2541baSDirk Eibach #define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F 3251d2541baSDirk Eibach #define CONFIG_SYS_I2C_IHS_CH3_1 3261d2541baSDirk Eibach #define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000 3271d2541baSDirk Eibach #define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F 3281d2541baSDirk Eibach #endif 3291d2541baSDirk Eibach 330a3f9d6c7SDirk Eibach /* 331a3f9d6c7SDirk Eibach * Software (bit-bang) I2C driver configuration 332a3f9d6c7SDirk Eibach */ 333a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT 334a3f9d6c7SDirk Eibach #define CONFIG_SOFT_I2C_READ_REPEATED_START 335a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SPEED 50000 336a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F 337a3f9d6c7SDirk Eibach #define I2C_SOFT_DECLARATIONS2 338a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 339a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F 340a3f9d6c7SDirk Eibach #define I2C_SOFT_DECLARATIONS3 341a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000 342a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F 343a3f9d6c7SDirk Eibach #define I2C_SOFT_DECLARATIONS4 344a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 345a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F 3461d2541baSDirk Eibach #if defined(CONFIG_STRIDER_CON) || defined(CONFIG_STRIDER_CON_DP) 347a3f9d6c7SDirk Eibach #define I2C_SOFT_DECLARATIONS5 348a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000 349a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F 350a3f9d6c7SDirk Eibach #define I2C_SOFT_DECLARATIONS6 351a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SPEED_6 50000 352a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F 353a3f9d6c7SDirk Eibach #define I2C_SOFT_DECLARATIONS7 354a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SPEED_7 50000 355a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F 356a3f9d6c7SDirk Eibach #define I2C_SOFT_DECLARATIONS8 357a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000 358a3f9d6c7SDirk Eibach #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F 359a3f9d6c7SDirk Eibach #endif 3601d2541baSDirk Eibach #ifdef CONFIG_STRIDER_CON_DP 3611d2541baSDirk Eibach #define I2C_SOFT_DECLARATIONS9 3621d2541baSDirk Eibach #define CONFIG_SYS_I2C_SOFT_SPEED_9 50000 3631d2541baSDirk Eibach #define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F 3641d2541baSDirk Eibach #define I2C_SOFT_DECLARATIONS10 3651d2541baSDirk Eibach #define CONFIG_SYS_I2C_SOFT_SPEED_10 50000 3661d2541baSDirk Eibach #define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F 3671d2541baSDirk Eibach #define I2C_SOFT_DECLARATIONS11 3681d2541baSDirk Eibach #define CONFIG_SYS_I2C_SOFT_SPEED_11 50000 3691d2541baSDirk Eibach #define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F 3701d2541baSDirk Eibach #define I2C_SOFT_DECLARATIONS12 3711d2541baSDirk Eibach #define CONFIG_SYS_I2C_SOFT_SPEED_12 50000 3721d2541baSDirk Eibach #define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F 3731d2541baSDirk Eibach #endif 374a3f9d6c7SDirk Eibach 375a3f9d6c7SDirk Eibach #ifdef CONFIG_STRIDER_CON 376a3f9d6c7SDirk Eibach #define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8} 377a3f9d6c7SDirk Eibach #define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8} 378a3f9d6c7SDirk Eibach #define CONFIG_SYS_ADV7611_I2C {5, 6, 7, 8} 379a3f9d6c7SDirk Eibach #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 380a3f9d6c7SDirk Eibach #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \ 381a3f9d6c7SDirk Eibach {12, 0x4c} } 3821d2541baSDirk Eibach #elif defined(CONFIG_STRIDER_CON_DP) 3831d2541baSDirk Eibach #define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20} 3841d2541baSDirk Eibach #define CONFIG_SYS_CH7301_I2C {1, 3, 5, 7} 3851d2541baSDirk Eibach #define CONFIG_SYS_ADV7611_I2C {1, 3, 5, 7} 3861d2541baSDirk Eibach #define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8} 3871d2541baSDirk Eibach #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \ 3881d2541baSDirk Eibach {12, 0x4c} } 389145510ccSDirk Eibach #elif defined(CONFIG_STRIDER_CPU_DP) 390145510ccSDirk Eibach #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4} 391145510ccSDirk Eibach #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4} 392145510ccSDirk Eibach #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 393145510ccSDirk Eibach #define CONFIG_STRIDER_FANS { {6, 0x4c}, {7, 0x4c}, \ 394145510ccSDirk Eibach {8, 0x4c} } 395a3f9d6c7SDirk Eibach #else 396a3f9d6c7SDirk Eibach #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4} 397a3f9d6c7SDirk Eibach #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4} 398a3f9d6c7SDirk Eibach #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 399a3f9d6c7SDirk Eibach #define CONFIG_STRIDER_FANS { {2, 0x18}, {3, 0x18}, \ 400a3f9d6c7SDirk Eibach {4, 0x18} } 401a3f9d6c7SDirk Eibach #endif 402a3f9d6c7SDirk Eibach 403a3f9d6c7SDirk Eibach #ifndef __ASSEMBLY__ 404a3f9d6c7SDirk Eibach void fpga_gpio_set(unsigned int bus, int pin); 405a3f9d6c7SDirk Eibach void fpga_gpio_clear(unsigned int bus, int pin); 406a3f9d6c7SDirk Eibach int fpga_gpio_get(unsigned int bus, int pin); 4071d2541baSDirk Eibach void fpga_control_set(unsigned int bus, int pin); 4081d2541baSDirk Eibach void fpga_control_clear(unsigned int bus, int pin); 409a3f9d6c7SDirk Eibach #endif 410a3f9d6c7SDirk Eibach 411a3f9d6c7SDirk Eibach #ifdef CONFIG_STRIDER_CON 412a3f9d6c7SDirk Eibach #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040) 413a3f9d6c7SDirk Eibach #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020) 414a3f9d6c7SDirk Eibach #define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \ 415a3f9d6c7SDirk Eibach (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR) 4161d2541baSDirk Eibach #elif defined(CONFIG_STRIDER_CON_DP) 4171d2541baSDirk Eibach #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200) 4181d2541baSDirk Eibach #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100) 4191d2541baSDirk Eibach #define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4) 420a3f9d6c7SDirk Eibach #else 421a3f9d6c7SDirk Eibach #define I2C_SDA_GPIO 0x0040 422a3f9d6c7SDirk Eibach #define I2C_SCL_GPIO 0x0020 423a3f9d6c7SDirk Eibach #define I2C_FPGA_IDX I2C_ADAP_HWNR 424a3f9d6c7SDirk Eibach #endif 4251d2541baSDirk Eibach 4261d2541baSDirk Eibach #ifdef CONFIG_STRIDER_CON_DP 4271d2541baSDirk Eibach #define I2C_ACTIVE \ 4281d2541baSDirk Eibach do { \ 4291d2541baSDirk Eibach if (I2C_ADAP_HWNR > 7) \ 4301d2541baSDirk Eibach fpga_control_set(I2C_FPGA_IDX, 0x0004); \ 4311d2541baSDirk Eibach else \ 4321d2541baSDirk Eibach fpga_control_clear(I2C_FPGA_IDX, 0x0004); \ 4331d2541baSDirk Eibach } while (0) 4341d2541baSDirk Eibach #else 435a3f9d6c7SDirk Eibach #define I2C_ACTIVE { } 4361d2541baSDirk Eibach #endif 4371d2541baSDirk Eibach 438a3f9d6c7SDirk Eibach #define I2C_TRISTATE { } 439a3f9d6c7SDirk Eibach #define I2C_READ \ 440a3f9d6c7SDirk Eibach (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0) 441a3f9d6c7SDirk Eibach #define I2C_SDA(bit) \ 442a3f9d6c7SDirk Eibach do { \ 443a3f9d6c7SDirk Eibach if (bit) \ 444a3f9d6c7SDirk Eibach fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \ 445a3f9d6c7SDirk Eibach else \ 446a3f9d6c7SDirk Eibach fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \ 447a3f9d6c7SDirk Eibach } while (0) 448a3f9d6c7SDirk Eibach #define I2C_SCL(bit) \ 449a3f9d6c7SDirk Eibach do { \ 450a3f9d6c7SDirk Eibach if (bit) \ 451a3f9d6c7SDirk Eibach fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \ 452a3f9d6c7SDirk Eibach else \ 453a3f9d6c7SDirk Eibach fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \ 454a3f9d6c7SDirk Eibach } while (0) 455a3f9d6c7SDirk Eibach #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ 456a3f9d6c7SDirk Eibach 457a3f9d6c7SDirk Eibach /* 458a3f9d6c7SDirk Eibach * Software (bit-bang) MII driver configuration 459a3f9d6c7SDirk Eibach */ 460a3f9d6c7SDirk Eibach #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 461a3f9d6c7SDirk Eibach #define CONFIG_BITBANGMII_MULTI 462a3f9d6c7SDirk Eibach 463a3f9d6c7SDirk Eibach /* 464a3f9d6c7SDirk Eibach * OSD Setup 465a3f9d6c7SDirk Eibach */ 466a3f9d6c7SDirk Eibach #define CONFIG_SYS_OSD_SCREENS 1 467a3f9d6c7SDirk Eibach #define CONFIG_SYS_DP501_DIFFERENTIAL 468a3f9d6c7SDirk Eibach #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ 469a3f9d6c7SDirk Eibach 4701d2541baSDirk Eibach #ifdef CONFIG_STRIDER_CON_DP 4711d2541baSDirk Eibach #define CONFIG_SYS_OSD_DH 4721d2541baSDirk Eibach #endif 4731d2541baSDirk Eibach 474a3f9d6c7SDirk Eibach /* 475a3f9d6c7SDirk Eibach * General PCI 476a3f9d6c7SDirk Eibach * Addresses are mapped 1-1. 477a3f9d6c7SDirk Eibach */ 478a3f9d6c7SDirk Eibach #define CONFIG_SYS_PCIE1_BASE 0xA0000000 479a3f9d6c7SDirk Eibach #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 480a3f9d6c7SDirk Eibach #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 481a3f9d6c7SDirk Eibach #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 482a3f9d6c7SDirk Eibach #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 483a3f9d6c7SDirk Eibach #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 484a3f9d6c7SDirk Eibach #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 485a3f9d6c7SDirk Eibach #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 486a3f9d6c7SDirk Eibach #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 487a3f9d6c7SDirk Eibach 488a3f9d6c7SDirk Eibach /* enable PCIE clock */ 489a3f9d6c7SDirk Eibach #define CONFIG_SYS_SCCR_PCIEXP1CM 1 490a3f9d6c7SDirk Eibach 491a3f9d6c7SDirk Eibach #define CONFIG_PCI_INDIRECT_BRIDGE 492a3f9d6c7SDirk Eibach #define CONFIG_PCIE 493a3f9d6c7SDirk Eibach 494a3f9d6c7SDirk Eibach #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 495a3f9d6c7SDirk Eibach #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 496a3f9d6c7SDirk Eibach 497a3f9d6c7SDirk Eibach /* 498a3f9d6c7SDirk Eibach * TSEC 499a3f9d6c7SDirk Eibach */ 500a3f9d6c7SDirk Eibach #define CONFIG_SYS_TSEC1_OFFSET 0x24000 501a3f9d6c7SDirk Eibach #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 502a3f9d6c7SDirk Eibach 503a3f9d6c7SDirk Eibach /* 504a3f9d6c7SDirk Eibach * TSEC ethernet configuration 505a3f9d6c7SDirk Eibach */ 506a3f9d6c7SDirk Eibach #define CONFIG_MII 1 /* MII PHY management */ 507a3f9d6c7SDirk Eibach #define CONFIG_TSEC1 508a3f9d6c7SDirk Eibach #define CONFIG_TSEC1_NAME "eTSEC0" 509a3f9d6c7SDirk Eibach #define TSEC1_PHY_ADDR 1 510a3f9d6c7SDirk Eibach #define TSEC1_PHYIDX 0 511a3f9d6c7SDirk Eibach #define TSEC1_FLAGS 0 512a3f9d6c7SDirk Eibach 513a3f9d6c7SDirk Eibach /* Options are: eTSEC[0-1] */ 514a3f9d6c7SDirk Eibach #define CONFIG_ETHPRIME "eTSEC0" 515a3f9d6c7SDirk Eibach 516a3f9d6c7SDirk Eibach /* 517a3f9d6c7SDirk Eibach * Environment 518a3f9d6c7SDirk Eibach */ 519a3f9d6c7SDirk Eibach #if 1 520a3f9d6c7SDirk Eibach #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 521a3f9d6c7SDirk Eibach CONFIG_SYS_MONITOR_LEN) 522a3f9d6c7SDirk Eibach #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ 523a3f9d6c7SDirk Eibach #define CONFIG_ENV_SIZE 0x2000 524a3f9d6c7SDirk Eibach #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 525a3f9d6c7SDirk Eibach #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 526a3f9d6c7SDirk Eibach #else 527a3f9d6c7SDirk Eibach #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 528a3f9d6c7SDirk Eibach #endif 529a3f9d6c7SDirk Eibach 530a3f9d6c7SDirk Eibach #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 531a3f9d6c7SDirk Eibach #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 532a3f9d6c7SDirk Eibach 533a3f9d6c7SDirk Eibach /* 534a3f9d6c7SDirk Eibach * Command line configuration. 535a3f9d6c7SDirk Eibach */ 536a3f9d6c7SDirk Eibach 537a3f9d6c7SDirk Eibach /* 538a3f9d6c7SDirk Eibach * Miscellaneous configurable options 539a3f9d6c7SDirk Eibach */ 540a3f9d6c7SDirk Eibach #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 541a3f9d6c7SDirk Eibach #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 542a3f9d6c7SDirk Eibach 543a3f9d6c7SDirk Eibach #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 544a3f9d6c7SDirk Eibach 545a3f9d6c7SDirk Eibach #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 546a3f9d6c7SDirk Eibach 547a3f9d6c7SDirk Eibach /* 548a3f9d6c7SDirk Eibach * For booting Linux, the board info and command line data 549a3f9d6c7SDirk Eibach * have to be in the first 256 MB of memory, since this is 550a3f9d6c7SDirk Eibach * the maximum mapped by the Linux kernel during initialization. 551a3f9d6c7SDirk Eibach */ 552a3f9d6c7SDirk Eibach #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 553a3f9d6c7SDirk Eibach 554a3f9d6c7SDirk Eibach /* 555a3f9d6c7SDirk Eibach * Core HID Setup 556a3f9d6c7SDirk Eibach */ 557a3f9d6c7SDirk Eibach #define CONFIG_SYS_HID0_INIT 0x000000000 558a3f9d6c7SDirk Eibach #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 559a3f9d6c7SDirk Eibach HID0_ENABLE_INSTRUCTION_CACHE | \ 560a3f9d6c7SDirk Eibach HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) 561a3f9d6c7SDirk Eibach #define CONFIG_SYS_HID2 HID2_HBE 562a3f9d6c7SDirk Eibach 563a3f9d6c7SDirk Eibach /* 564a3f9d6c7SDirk Eibach * MMU Setup 565a3f9d6c7SDirk Eibach */ 566a3f9d6c7SDirk Eibach 567a3f9d6c7SDirk Eibach /* DDR: cache cacheable */ 568a3f9d6c7SDirk Eibach #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 569a3f9d6c7SDirk Eibach BATL_MEMCOHERENCE) 570a3f9d6c7SDirk Eibach #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ 571a3f9d6c7SDirk Eibach BATU_VS | BATU_VP) 572a3f9d6c7SDirk Eibach #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 573a3f9d6c7SDirk Eibach #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 574a3f9d6c7SDirk Eibach 575a3f9d6c7SDirk Eibach /* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */ 576a3f9d6c7SDirk Eibach #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 577a3f9d6c7SDirk Eibach BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 578a3f9d6c7SDirk Eibach #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ 579a3f9d6c7SDirk Eibach BATU_VP) 580a3f9d6c7SDirk Eibach #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 581a3f9d6c7SDirk Eibach #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 582a3f9d6c7SDirk Eibach 583a3f9d6c7SDirk Eibach /* FLASH: icache cacheable, but dcache-inhibit and guarded */ 584a3f9d6c7SDirk Eibach #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 585a3f9d6c7SDirk Eibach BATL_MEMCOHERENCE) 586a3f9d6c7SDirk Eibach #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ 587a3f9d6c7SDirk Eibach BATU_VS | BATU_VP) 588a3f9d6c7SDirk Eibach #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ 589a3f9d6c7SDirk Eibach BATL_CACHEINHIBIT | \ 590a3f9d6c7SDirk Eibach BATL_GUARDEDSTORAGE) 591a3f9d6c7SDirk Eibach #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 592a3f9d6c7SDirk Eibach 593a3f9d6c7SDirk Eibach /* Stack in dcache: cacheable, no memory coherence */ 594a3f9d6c7SDirk Eibach #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) 595a3f9d6c7SDirk Eibach #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ 596a3f9d6c7SDirk Eibach BATU_VS | BATU_VP) 597a3f9d6c7SDirk Eibach #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 598a3f9d6c7SDirk Eibach #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 599a3f9d6c7SDirk Eibach 600a3f9d6c7SDirk Eibach /* 601a3f9d6c7SDirk Eibach * Environment Configuration 602a3f9d6c7SDirk Eibach */ 603a3f9d6c7SDirk Eibach 604a3f9d6c7SDirk Eibach #define CONFIG_ENV_OVERWRITE 605a3f9d6c7SDirk Eibach 606a3f9d6c7SDirk Eibach #if defined(CONFIG_TSEC_ENET) 607a3f9d6c7SDirk Eibach #define CONFIG_HAS_ETH0 608a3f9d6c7SDirk Eibach #endif 609a3f9d6c7SDirk Eibach 610a3f9d6c7SDirk Eibach #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 611a3f9d6c7SDirk Eibach 612a3f9d6c7SDirk Eibach 613*5bc0543dSMario Six #define CONFIG_HOSTNAME "hrcon" 614a3f9d6c7SDirk Eibach #define CONFIG_ROOTPATH "/opt/nfsroot" 615a3f9d6c7SDirk Eibach #define CONFIG_BOOTFILE "uImage" 616a3f9d6c7SDirk Eibach 617a3f9d6c7SDirk Eibach #define CONFIG_PREBOOT /* enable preboot variable */ 618a3f9d6c7SDirk Eibach 619a3f9d6c7SDirk Eibach #define CONFIG_EXTRA_ENV_SETTINGS \ 620a3f9d6c7SDirk Eibach "netdev=eth0\0" \ 621a3f9d6c7SDirk Eibach "consoledev=ttyS1\0" \ 622a3f9d6c7SDirk Eibach "u-boot=u-boot.bin\0" \ 623a3f9d6c7SDirk Eibach "kernel_addr=1000000\0" \ 624a3f9d6c7SDirk Eibach "fdt_addr=C00000\0" \ 625a3f9d6c7SDirk Eibach "fdtfile=hrcon.dtb\0" \ 626a3f9d6c7SDirk Eibach "load=tftp ${loadaddr} ${u-boot}\0" \ 627a3f9d6c7SDirk Eibach "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 628a3f9d6c7SDirk Eibach " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ 629a3f9d6c7SDirk Eibach " +${filesize};cp.b ${fileaddr} " \ 630a3f9d6c7SDirk Eibach __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 631a3f9d6c7SDirk Eibach "upd=run load update\0" \ 632a3f9d6c7SDirk Eibach 633a3f9d6c7SDirk Eibach #define CONFIG_NFSBOOTCOMMAND \ 634a3f9d6c7SDirk Eibach "setenv bootargs root=/dev/nfs rw " \ 635a3f9d6c7SDirk Eibach "nfsroot=$serverip:$rootpath " \ 636a3f9d6c7SDirk Eibach "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 637a3f9d6c7SDirk Eibach "console=$consoledev,$baudrate $othbootargs;" \ 638a3f9d6c7SDirk Eibach "tftp ${kernel_addr} $bootfile;" \ 639a3f9d6c7SDirk Eibach "tftp ${fdt_addr} $fdtfile;" \ 640a3f9d6c7SDirk Eibach "bootm ${kernel_addr} - ${fdt_addr}" 641a3f9d6c7SDirk Eibach 642a3f9d6c7SDirk Eibach #define CONFIG_MMCBOOTCOMMAND \ 643a3f9d6c7SDirk Eibach "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ 644a3f9d6c7SDirk Eibach "console=$consoledev,$baudrate $othbootargs;" \ 645a3f9d6c7SDirk Eibach "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \ 646a3f9d6c7SDirk Eibach "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \ 647a3f9d6c7SDirk Eibach "bootm ${kernel_addr} - ${fdt_addr}" 648a3f9d6c7SDirk Eibach 649a3f9d6c7SDirk Eibach #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND 650a3f9d6c7SDirk Eibach 651a3f9d6c7SDirk Eibach #endif /* __CONFIG_H */ 652