xref: /openbmc/u-boot/include/configs/stout.h (revision 679590eb)
1 /*
2  * include/configs/stout.h
3  *     This file is Stout board configuration.
4  *
5  * Copyright (C) 2015 Renesas Electronics Europe GmbH
6  * Copyright (C) 2015 Renesas Electronics Corporation
7  * Copyright (C) 2015 Cogent Embedded, Inc.
8  *
9  * SPDX-License-Identifier: GPL-2.0
10  */
11 
12 #ifndef __STOUT_H
13 #define __STOUT_H
14 
15 #undef DEBUG
16 #define CONFIG_R8A7790
17 #define CONFIG_ARCH_RMOBILE_BOARD_STRING "Stout"
18 
19 #include "rcar-gen2-common.h"
20 
21 #if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
22 #define CONFIG_SYS_TEXT_BASE	0xB0000000
23 #else
24 #define CONFIG_SYS_TEXT_BASE	0xE8080000
25 #endif
26 
27 /* STACK */
28 #if defined(CONFIGF_RMOBILE_EXTRAM_BOOT)
29 #define CONFIG_SYS_INIT_SP_ADDR		0xB003FFFC
30 #else
31 #define CONFIG_SYS_INIT_SP_ADDR		0xE827FFFC
32 #endif
33 #define STACK_AREA_SIZE			0xC000
34 #define LOW_LEVEL_MERAM_STACK	\
35 		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
36 
37 /* MEMORY */
38 #define RCAR_GEN2_SDRAM_BASE		0x40000000
39 #define RCAR_GEN2_SDRAM_SIZE		(1024u * 1024 * 1024)
40 #define RCAR_GEN2_UBOOT_SDRAM_SIZE	(512 * 1024 * 1024)
41 
42 /* SCIF */
43 #define CONFIG_SCIF_A
44 
45 /* SPI */
46 #define CONFIG_SPI
47 #define CONFIG_SH_QSPI
48 #define CONFIG_SPI_FLASH_QUAD
49 
50 /* SH Ether */
51 #define CONFIG_SH_ETHER
52 #define CONFIG_SH_ETHER_USE_PORT	0
53 #define CONFIG_SH_ETHER_PHY_ADDR	0x1
54 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
55 #define CONFIG_SH_ETHER_ALIGNE_SIZE	64
56 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
57 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
58 #define CONFIG_PHYLIB
59 #define CONFIG_PHY_MICREL
60 #define CONFIG_BITBANGMII
61 #define CONFIG_BITBANGMII_MULTI
62 
63 /* I2C */
64 #define CONFIG_SYS_I2C
65 #define CONFIG_SYS_I2C_RCAR
66 #define CONFIG_SYS_RCAR_I2C0_SPEED	400000
67 #define CONFIG_SYS_RCAR_I2C1_SPEED	400000
68 #define CONFIG_SYS_RCAR_I2C2_SPEED	400000
69 #define CONFIG_SYS_RCAR_I2C3_SPEED	400000
70 #define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS	4
71 
72 #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
73 
74 /* Board Clock */
75 #define RMOBILE_XTAL_CLK	20000000u
76 #define CONFIG_SYS_CLK_FREQ	RMOBILE_XTAL_CLK
77 #define CONFIG_SH_TMU_CLK_FREQ	(CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
78 #define CONFIG_PLL1_CLK_FREQ	(CONFIG_SYS_CLK_FREQ * 156 / 2)
79 #define CONFIG_PLL1_DIV2_CLK_FREQ	(CONFIG_PLL1_CLK_FREQ / 2)
80 #define CONFIG_MP_CLK_FREQ	(CONFIG_PLL1_DIV2_CLK_FREQ / 15)
81 #define CONFIG_HP_CLK_FREQ	(CONFIG_PLL1_CLK_FREQ / 12)
82 
83 #define CONFIG_SYS_TMU_CLK_DIV	4
84 
85 /* USB */
86 #define CONFIG_USB_EHCI_RMOBILE
87 #define CONFIG_USB_MAX_CONTROLLER_COUNT	3
88 
89 /* Module stop status bits */
90 /* INTC-RT */
91 #define CONFIG_SMSTP0_ENA	0x00400000
92 /* MSIF, SCIFA0 */
93 #define CONFIG_SMSTP2_ENA	0x00002010
94 /* INTC-SYS, IRQC */
95 #define CONFIG_SMSTP4_ENA	0x00000180
96 
97 /* SDHI */
98 #define CONFIG_SH_SDHI_FREQ	97500000
99 
100 #endif	/* __STOUT_H */
101