1 /* 2 * include/configs/stout.h 3 * This file is Stout board configuration. 4 * 5 * Copyright (C) 2015 Renesas Electronics Europe GmbH 6 * Copyright (C) 2015 Renesas Electronics Corporation 7 * Copyright (C) 2015 Cogent Embedded, Inc. 8 * 9 * SPDX-License-Identifier: GPL-2.0 10 */ 11 12 #ifndef __STOUT_H 13 #define __STOUT_H 14 15 #undef DEBUG 16 #define CONFIG_R8A7790 17 #define CONFIG_RMOBILE_BOARD_STRING "Stout" 18 19 #include "rcar-gen2-common.h" 20 21 /* #define CONFIG_BOARD_LATE_INIT */ 22 23 #if defined(CONFIG_RMOBILE_EXTRAM_BOOT) 24 #define CONFIG_SYS_TEXT_BASE 0xB0000000 25 #else 26 #define CONFIG_SYS_TEXT_BASE 0xE8080000 27 #endif 28 29 /* STACK */ 30 #if defined(CONFIGF_RMOBILE_EXTRAM_BOOT) 31 #define CONFIG_SYS_INIT_SP_ADDR 0xB003FFFC 32 #else 33 #define CONFIG_SYS_INIT_SP_ADDR 0xE827FFFC 34 #endif 35 #define STACK_AREA_SIZE 0xC000 36 #define LOW_LEVEL_MERAM_STACK \ 37 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) 38 39 /* MEMORY */ 40 #define RCAR_GEN2_SDRAM_BASE 0x40000000 41 #define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) 42 #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) 43 44 /* SCIF */ 45 #define CONFIG_SCIF_CONSOLE 46 #define CONFIG_SCIF_A 47 48 /* SPI */ 49 #define CONFIG_SPI 50 #define CONFIG_SH_QSPI 51 #define CONFIG_SPI_FLASH_QUAD 52 #define CONFIG_SYS_NO_FLASH 53 54 /* SH Ether */ 55 #define CONFIG_SH_ETHER 56 #define CONFIG_SH_ETHER_USE_PORT 0 57 #define CONFIG_SH_ETHER_PHY_ADDR 0x1 58 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII 59 #define CONFIG_SH_ETHER_ALIGNE_SIZE 64 60 #define CONFIG_SH_ETHER_CACHE_WRITEBACK 61 #define CONFIG_SH_ETHER_CACHE_INVALIDATE 62 #define CONFIG_PHYLIB 63 #define CONFIG_PHY_MICREL 64 #define CONFIG_BITBANGMII 65 #define CONFIG_BITBANGMII_MULTI 66 67 /* I2C */ 68 #define CONFIG_SYS_I2C 69 #define CONFIG_SYS_I2C_RCAR 70 #define CONFIG_SYS_RCAR_I2C0_SPEED 400000 71 #define CONFIG_SYS_RCAR_I2C1_SPEED 400000 72 #define CONFIG_SYS_RCAR_I2C2_SPEED 400000 73 #define CONFIG_SYS_RCAR_I2C3_SPEED 400000 74 #define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4 75 76 #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ 77 78 /* Board Clock */ 79 #define RMOBILE_XTAL_CLK 20000000u 80 #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK 81 #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ 82 #define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) 83 #define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2) 84 #define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15) 85 #define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12) 86 87 #define CONFIG_SYS_TMU_CLK_DIV 4 88 89 /* USB */ 90 #define CONFIG_USB_EHCI 91 #define CONFIG_USB_EHCI_RMOBILE 92 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 93 #define CONFIG_USB_STORAGE 94 95 /* MMC */ 96 #define CONFIG_MMC 97 #define CONFIG_GENERIC_MMC 98 99 /* Module stop status bits */ 100 /* INTC-RT */ 101 #define CONFIG_SMSTP0_ENA 0x00400000 102 /* MSIF, SCIFA0 */ 103 #define CONFIG_SMSTP2_ENA 0x00002010 104 /* INTC-SYS, IRQC */ 105 #define CONFIG_SMSTP4_ENA 0x00000180 106 107 /* SDHI */ 108 #define CONFIG_SH_SDHI_FREQ 97500000 109 110 #endif /* __STOUT_H */ 111