1 /* 2 * Sysam stmark2 board configuration 3 * 4 * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __STMARK2_CONFIG_H 10 #define __STMARK2_CONFIG_H 11 12 #define CONFIG_HOSTNAME stmark2 13 14 #define CONFIG_MCFUART 15 #define CONFIG_SYS_UART_PORT 0 16 #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } 17 18 #define LDS_BOARD_TEXT \ 19 board/sysam/stmark2/sbf_dram_init.o (.text*) 20 21 #define CONFIG_TIMESTAMP 22 23 #define CONFIG_BOOTARGS \ 24 "console=ttyS0,115200 root=/dev/ram0 rw " \ 25 "rootfstype=ramfs " \ 26 "rdinit=/bin/init " \ 27 "devtmpfs.mount=1" 28 29 #define CONFIG_BOOTCOMMAND \ 30 "sf probe 0:1 50000000; " \ 31 "sf read ${loadaddr} 0x100000 ${kern_size}; " \ 32 "bootm ${loadaddr}" 33 34 #define CONFIG_EXTRA_ENV_SETTINGS \ 35 "kern_size=0x700000\0" \ 36 "loadaddr=0x40001000\0" \ 37 "-(rootfs)\0" \ 38 "update_uboot=loady ${loadaddr}; " \ 39 "sf probe 0:1 50000000; " \ 40 "sf erase 0 0x80000; " \ 41 "sf write ${loadaddr} 0 ${filesize}\0" \ 42 "update_kernel=loady ${loadaddr}; " \ 43 "setenv kern_size ${filesize}; saveenv; " \ 44 "sf probe 0:1 50000000; " \ 45 "sf erase 0x100000 0x700000; " \ 46 "sf write ${loadaddr} 0x100000 ${filesize}\0" \ 47 "update_rootfs=loady ${loadaddr}; " \ 48 "sf probe 0:1 50000000; " \ 49 "sf erase 0x00800000 0x100000; " \ 50 "sf write ${loadaddr} 0x00800000 ${filesize}\0" \ 51 "" 52 53 /* Realtime clock */ 54 #undef CONFIG_MCFRTC 55 #define CONFIG_RTC_MCFRRTC 56 #define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000 57 58 /* spi not partitions */ 59 #define CONFIG_MTD_DEVICE 60 #define CONFIG_JFFS2_CMDLINE 61 #define CONFIG_JFFS2_DEV "nor0" 62 63 /* Timer */ 64 #define CONFIG_MCFTMR 65 #undef CONFIG_MCFPIT 66 67 /* DSPI and Serial Flash */ 68 #define CONFIG_CF_DSPI 69 #define CONFIG_SF_DEFAULT_SPEED 50000000 70 #define CONFIG_SERIAL_FLASH 71 #define CONFIG_HARD_SPI 72 #define CONFIG_SPI_FLASH_ISSI 73 #define CONFIG_ENV_SPI_BUS 0 74 #define CONFIG_ENV_SPI_CS 1 75 76 #define CONFIG_SYS_SBFHDR_SIZE 0x7 77 78 #define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 79 DSPI_CTAR_PCSSCK_1CLK | \ 80 DSPI_CTAR_PASC(0) | \ 81 DSPI_CTAR_PDT(0) | \ 82 DSPI_CTAR_CSSCK(0) | \ 83 DSPI_CTAR_ASC(0) | \ 84 DSPI_CTAR_DT(1) | \ 85 DSPI_CTAR_BR(6)) 86 #define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) 87 #define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) 88 89 /* Input, PCI, Flexbus, and VCO */ 90 #define CONFIG_EXTRA_CLOCK 91 92 #define CONFIG_PRAM 2048 /* 2048 KB */ 93 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 94 95 /* Print Buffer Size */ 96 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 97 sizeof(CONFIG_SYS_PROMPT) + 16) 98 #define CONFIG_SYS_MAXARGS 16 99 /* Boot Argument Buffer Size */ 100 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 101 102 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 103 #define CONFIG_SYS_MBAR 0xFC000000 104 105 /* 106 * Definitions for initial stack pointer and data area (in internal SRAM) 107 */ 108 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 109 /* End of used area in internal SRAM */ 110 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 111 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 112 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ 113 GENERATED_GBL_DATA_SIZE) - 32) 114 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 115 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 116 117 /* 118 * Start addresses for the final memory configuration 119 * (Set up by the startup code) 120 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 121 */ 122 #define CONFIG_SYS_SDRAM_BASE 0x40000000 123 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ 124 125 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400) 126 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 127 #define CONFIG_SYS_DRAM_TEST 128 129 #if defined(CONFIG_CF_SBF) 130 #define CONFIG_SERIAL_BOOT 131 #endif 132 133 #if defined(CONFIG_SERIAL_BOOT) 134 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 135 #else 136 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 137 #endif 138 139 #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) 140 /* Reserve 256 kB for Monitor */ 141 #define CONFIG_SYS_MONITOR_LEN (256 << 10) 142 /* Reserve 256 kB for malloc() */ 143 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 144 145 /* 146 * For booting Linux, the board info and command line data 147 * have to be in the first 8 MB of memory, since this is 148 * the maximum mapped by the Linux kernel during initialization ?? 149 */ 150 /* Initial Memory map for Linux */ 151 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ 152 (CONFIG_SYS_SDRAM_SIZE << 20)) 153 154 /* Configuration for environment 155 * Environment is embedded in u-boot in the second sector of the flash 156 */ 157 158 #if defined(CONFIG_CF_SBF) 159 #define CONFIG_ENV_IS_IN_SPI_FLASH 1 160 #define CONFIG_ENV_SPI_CS 1 161 #define CONFIG_ENV_OFFSET 0x40000 162 #define CONFIG_ENV_SIZE 0x2000 163 #define CONFIG_ENV_SECT_SIZE 0x10000 164 #endif 165 166 #undef CONFIG_ENV_OVERWRITE 167 168 /* Cache Configuration */ 169 #define CONFIG_SYS_CACHELINE_SIZE 16 170 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 171 CONFIG_SYS_INIT_RAM_SIZE - 8) 172 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 173 CONFIG_SYS_INIT_RAM_SIZE - 4) 174 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 175 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 176 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 177 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 178 CF_ACR_EN | CF_ACR_SM_ALL) 179 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 180 CF_CACR_ICINVA | CF_CACR_EUSP) 181 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 182 CF_CACR_DEC | CF_CACR_DDCM_P | \ 183 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 184 185 #define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 186 CONFIG_SYS_INIT_RAM_SIZE - 12) 187 188 #endif /* __STMARK2_CONFIG_H */ 189