1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Sysam stmark2 board configuration 4 * 5 * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it> 6 */ 7 8 #ifndef __STMARK2_CONFIG_H 9 #define __STMARK2_CONFIG_H 10 11 #define CONFIG_HOSTNAME "stmark2" 12 13 #define CONFIG_MCFUART 14 #define CONFIG_SYS_UART_PORT 0 15 #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } 16 17 #define LDS_BOARD_TEXT \ 18 board/sysam/stmark2/sbf_dram_init.o (.text*) 19 20 #define CONFIG_TIMESTAMP 21 22 #define CONFIG_BOOTARGS \ 23 "console=ttyS0,115200 root=/dev/ram0 rw " \ 24 "rootfstype=ramfs " \ 25 "rdinit=/bin/init " \ 26 "devtmpfs.mount=1" 27 28 #define CONFIG_BOOTCOMMAND \ 29 "sf probe 0:1 50000000; " \ 30 "sf read ${loadaddr} 0x100000 ${kern_size}; " \ 31 "bootm ${loadaddr}" 32 33 #define CONFIG_EXTRA_ENV_SETTINGS \ 34 "kern_size=0x700000\0" \ 35 "loadaddr=0x40001000\0" \ 36 "-(rootfs)\0" \ 37 "update_uboot=loady ${loadaddr}; " \ 38 "sf probe 0:1 50000000; " \ 39 "sf erase 0 0x80000; " \ 40 "sf write ${loadaddr} 0 ${filesize}\0" \ 41 "update_kernel=loady ${loadaddr}; " \ 42 "setenv kern_size ${filesize}; saveenv; " \ 43 "sf probe 0:1 50000000; " \ 44 "sf erase 0x100000 0x700000; " \ 45 "sf write ${loadaddr} 0x100000 ${filesize}\0" \ 46 "update_rootfs=loady ${loadaddr}; " \ 47 "sf probe 0:1 50000000; " \ 48 "sf erase 0x00800000 0x100000; " \ 49 "sf write ${loadaddr} 0x00800000 ${filesize}\0" \ 50 "" 51 52 /* Realtime clock */ 53 #undef CONFIG_MCFRTC 54 #define CONFIG_RTC_MCFRRTC 55 #define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000 56 57 /* spi not partitions */ 58 #define CONFIG_JFFS2_CMDLINE 59 #define CONFIG_JFFS2_DEV "nor0" 60 61 /* Timer */ 62 #define CONFIG_MCFTMR 63 #undef CONFIG_MCFPIT 64 65 /* DSPI and Serial Flash */ 66 #define CONFIG_CF_DSPI 67 #define CONFIG_SF_DEFAULT_SPEED 50000000 68 #define CONFIG_SERIAL_FLASH 69 #define CONFIG_ENV_SPI_BUS 0 70 #define CONFIG_ENV_SPI_CS 1 71 72 #define CONFIG_SYS_SBFHDR_SIZE 0x7 73 74 #define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 75 DSPI_CTAR_PCSSCK_1CLK | \ 76 DSPI_CTAR_PASC(0) | \ 77 DSPI_CTAR_PDT(0) | \ 78 DSPI_CTAR_CSSCK(0) | \ 79 DSPI_CTAR_ASC(0) | \ 80 DSPI_CTAR_DT(1) | \ 81 DSPI_CTAR_BR(6)) 82 #define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) 83 #define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) 84 85 /* Input, PCI, Flexbus, and VCO */ 86 #define CONFIG_EXTRA_CLOCK 87 88 #define CONFIG_PRAM 2048 /* 2048 KB */ 89 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 90 91 /* Print Buffer Size */ 92 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 93 sizeof(CONFIG_SYS_PROMPT) + 16) 94 #define CONFIG_SYS_MAXARGS 16 95 /* Boot Argument Buffer Size */ 96 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 97 98 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 99 #define CONFIG_SYS_MBAR 0xFC000000 100 101 /* 102 * Definitions for initial stack pointer and data area (in internal SRAM) 103 */ 104 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 105 /* End of used area in internal SRAM */ 106 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 107 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 108 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ 109 GENERATED_GBL_DATA_SIZE) - 32) 110 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 111 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 112 113 /* 114 * Start addresses for the final memory configuration 115 * (Set up by the startup code) 116 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 117 */ 118 #define CONFIG_SYS_SDRAM_BASE 0x40000000 119 #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ 120 121 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400) 122 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 123 #define CONFIG_SYS_DRAM_TEST 124 125 #if defined(CONFIG_CF_SBF) 126 #define CONFIG_SERIAL_BOOT 127 #endif 128 129 #if defined(CONFIG_SERIAL_BOOT) 130 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 131 #else 132 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 133 #endif 134 135 #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) 136 /* Reserve 256 kB for Monitor */ 137 #define CONFIG_SYS_MONITOR_LEN (256 << 10) 138 /* Reserve 256 kB for malloc() */ 139 #define CONFIG_SYS_MALLOC_LEN (256 << 10) 140 141 /* 142 * For booting Linux, the board info and command line data 143 * have to be in the first 8 MB of memory, since this is 144 * the maximum mapped by the Linux kernel during initialization ?? 145 */ 146 /* Initial Memory map for Linux */ 147 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ 148 (CONFIG_SYS_SDRAM_SIZE << 20)) 149 150 /* Configuration for environment 151 * Environment is embedded in u-boot in the second sector of the flash 152 */ 153 154 #if defined(CONFIG_CF_SBF) 155 #define CONFIG_ENV_IS_IN_SPI_FLASH 1 156 #define CONFIG_ENV_SPI_CS 1 157 #define CONFIG_ENV_OFFSET 0x40000 158 #define CONFIG_ENV_SIZE 0x2000 159 #define CONFIG_ENV_SECT_SIZE 0x10000 160 #endif 161 162 #undef CONFIG_ENV_OVERWRITE 163 164 /* Cache Configuration */ 165 #define CONFIG_SYS_CACHELINE_SIZE 16 166 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 167 CONFIG_SYS_INIT_RAM_SIZE - 8) 168 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 169 CONFIG_SYS_INIT_RAM_SIZE - 4) 170 #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 171 #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 172 #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 173 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 174 CF_ACR_EN | CF_ACR_SM_ALL) 175 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 176 CF_CACR_ICINVA | CF_CACR_EUSP) 177 #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 178 CF_CACR_DEC | CF_CACR_DDCM_P | \ 179 CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 180 181 #define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 182 CONFIG_SYS_INIT_RAM_SIZE - 12) 183 184 #endif /* __STMARK2_CONFIG_H */ 185