1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2009 4 * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com> 5 */ 6 7 #ifndef _SPEAR_COMMON_H 8 #define _SPEAR_COMMON_H 9 /* 10 * Common configurations used for both spear3xx as well as spear6xx 11 */ 12 13 /* U-Boot Load Address */ 14 15 /* Ethernet driver configuration */ 16 #define CONFIG_MII 17 #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ 18 19 /* USBD driver configuration */ 20 #if defined(CONFIG_SPEAR_USBTTY) 21 #define CONFIG_DW_UDC 22 #define CONFIG_USB_DEVICE 23 #define CONFIG_USBD_HS 24 #define CONFIG_USB_TTY 25 26 #define CONFIG_USBD_PRODUCT_NAME "SPEAr SoC" 27 #define CONFIG_USBD_MANUFACTURER "ST Microelectronics" 28 29 #endif 30 31 #define CONFIG_EXTRA_ENV_USBTTY "usbtty=cdc_acm\0" 32 33 /* I2C driver configuration */ 34 #define CONFIG_SYS_I2C 35 #if defined(CONFIG_SPEAR600) 36 #define CONFIG_SYS_I2C_BASE 0xD0200000 37 #elif defined(CONFIG_SPEAR300) 38 #define CONFIG_SYS_I2C_BASE 0xD0180000 39 #elif defined(CONFIG_SPEAR310) 40 #define CONFIG_SYS_I2C_BASE 0xD0180000 41 #elif defined(CONFIG_SPEAR320) 42 #define CONFIG_SYS_I2C_BASE 0xD0180000 43 #endif 44 #define CONFIG_SYS_I2C_SPEED 400000 45 #define CONFIG_SYS_I2C_SLAVE 0x02 46 47 #define CONFIG_I2C_CHIPADDRESS 0x50 48 49 /* Timer, HZ specific defines */ 50 51 /* Flash configuration */ 52 #if defined(CONFIG_FLASH_PNOR) 53 #define CONFIG_SPEAR_EMI 54 #else 55 #define CONFIG_ST_SMI 56 #endif 57 58 #if defined(CONFIG_ST_SMI) 59 60 #define CONFIG_SYS_MAX_FLASH_BANKS 2 61 #define CONFIG_SYS_FLASH_BASE 0xF8000000 62 #define CONFIG_SYS_CS1_FLASH_BASE 0xF9000000 63 #define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000 64 #define CONFIG_SYS_FLASH_ADDR_BASE {CONFIG_SYS_FLASH_BASE, \ 65 CONFIG_SYS_CS1_FLASH_BASE} 66 #define CONFIG_SYS_MAX_FLASH_SECT 128 67 68 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ) 69 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ) 70 71 #endif 72 73 /* 74 * Serial Configuration (PL011) 75 * CONFIG_PL01x_PORTS is defined in specific files 76 */ 77 #define CONFIG_PL011_CLOCK (48 * 1000 * 1000) 78 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \ 79 57600, 115200 } 80 81 #define CONFIG_SYS_LOADS_BAUD_CHANGE 82 83 /* NAND FLASH Configuration */ 84 #define CONFIG_SYS_NAND_SELF_INIT 85 #define CONFIG_NAND_FSMC 86 #define CONFIG_SYS_MAX_NAND_DEVICE 1 87 #define CONFIG_SYS_NAND_ONFI_DETECTION 88 89 /* 90 * Default Environment Varible definitions 91 */ 92 #define CONFIG_ENV_OVERWRITE 93 94 /* 95 * U-Boot Environment placing definitions. 96 */ 97 #if defined(CONFIG_ENV_IS_IN_FLASH) 98 #ifdef CONFIG_ST_SMI 99 /* 100 * Environment is in serial NOR flash 101 */ 102 #define CONFIG_SYS_MONITOR_LEN 0x00040000 103 #define CONFIG_ENV_SECT_SIZE 0x00010000 104 #define CONFIG_FSMTDBLK "/dev/mtdblock3 " 105 106 #define CONFIG_BOOTCOMMAND "bootm 0xf8050000" 107 108 #elif defined(CONFIG_SPEAR_EMI) 109 /* 110 * Environment is in parallel NOR flash 111 */ 112 #define CONFIG_SYS_MONITOR_LEN 0x00060000 113 #define CONFIG_ENV_SECT_SIZE 0x00020000 114 #define CONFIG_FSMTDBLK "/dev/mtdblock3 " 115 116 #define CONFIG_BOOTCOMMAND "cp.b 0x50080000 0x1600000 " \ 117 "0x4C0000; bootm 0x1600000" 118 #endif 119 120 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ 121 CONFIG_SYS_MONITOR_LEN) 122 #elif defined(CONFIG_ENV_IS_IN_NAND) 123 /* 124 * Environment is in NAND 125 */ 126 127 #define CONFIG_ENV_OFFSET 0x60000 128 #define CONFIG_ENV_RANGE 0x10000 129 #define CONFIG_FSMTDBLK "/dev/mtdblock7 " 130 131 #define CONFIG_BOOTCOMMAND "nand read.jffs2 0x1600000 " \ 132 "0x80000 0x4C0000; " \ 133 "bootm 0x1600000" 134 #endif 135 136 #define CONFIG_NFSBOOTCOMMAND \ 137 "bootp; " \ 138 "setenv bootargs root=/dev/nfs rw " \ 139 "nfsroot=$(serverip):$(rootpath) " \ 140 "ip=$(ipaddr):$(serverip):$(gatewayip):" \ 141 "$(netmask):$(hostname):$(netdev):off " \ 142 "console=ttyAMA0,115200 $(othbootargs);" \ 143 "bootm; " 144 145 #define CONFIG_RAMBOOTCOMMAND \ 146 "setenv bootargs root=/dev/ram rw " \ 147 "console=ttyAMA0,115200 $(othbootargs);" \ 148 CONFIG_BOOTCOMMAND 149 150 #define CONFIG_ENV_SIZE 0x02000 151 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 152 153 /* Miscellaneous configurable options */ 154 #define CONFIG_ARCH_CPU_INIT 155 #define CONFIG_BOOT_PARAMS_ADDR 0x00000100 156 #define CONFIG_CMDLINE_TAG 157 #define CONFIG_SETUP_MEMORY_TAGS 158 #define CONFIG_MISC_INIT_R 159 160 #define CONFIG_SYS_MEMTEST_START 0x00800000 161 #define CONFIG_SYS_MEMTEST_END 0x04000000 162 #define CONFIG_SYS_MALLOC_LEN (1024*1024) 163 #define CONFIG_SYS_LOAD_ADDR 0x00800000 164 165 #define CONFIG_SYS_FLASH_EMPTY_INFO 166 167 /* Physical Memory Map */ 168 #define CONFIG_NR_DRAM_BANKS 1 169 #define PHYS_SDRAM_1 0x00000000 170 #define PHYS_SDRAM_1_MAXSIZE 0x40000000 171 172 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 173 #define CONFIG_SYS_INIT_RAM_ADDR 0xD2800000 174 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 175 176 #define CONFIG_SYS_INIT_SP_OFFSET \ 177 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 178 179 #define CONFIG_SYS_INIT_SP_ADDR \ 180 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 181 182 #endif 183