1 /*
2  * (C) Copyright 2009
3  * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #ifndef _SPEAR_COMMON_H
9 #define _SPEAR_COMMON_H
10 /*
11  * Common configurations used for both spear3xx as well as spear6xx
12  */
13 
14 /* U-Boot Load Address */
15 #define CONFIG_SYS_TEXT_BASE			0x00700000
16 
17 /* Ethernet driver configuration */
18 #define CONFIG_MII
19 #define CONFIG_PHY_RESET_DELAY			10000		/* in usec */
20 #define CONFIG_PHY_GIGE			/* Include GbE speed/duplex detection */
21 
22 /* USBD driver configuration */
23 #if defined(CONFIG_SPEAR_USBTTY)
24 #define CONFIG_DW_UDC
25 #define CONFIG_USB_DEVICE
26 #define CONFIG_USBD_HS
27 #define CONFIG_USB_TTY
28 
29 #define CONFIG_USBD_PRODUCT_NAME		"SPEAr SoC"
30 #define CONFIG_USBD_MANUFACTURER		"ST Microelectronics"
31 
32 #endif
33 
34 #define CONFIG_EXTRA_ENV_USBTTY			"usbtty=cdc_acm\0"
35 
36 /* I2C driver configuration */
37 #define CONFIG_SYS_I2C
38 #define CONFIG_SYS_I2C_DW
39 #if defined(CONFIG_SPEAR600)
40 #define CONFIG_SYS_I2C_BASE			0xD0200000
41 #elif defined(CONFIG_SPEAR300)
42 #define CONFIG_SYS_I2C_BASE			0xD0180000
43 #elif defined(CONFIG_SPEAR310)
44 #define CONFIG_SYS_I2C_BASE			0xD0180000
45 #elif defined(CONFIG_SPEAR320)
46 #define CONFIG_SYS_I2C_BASE			0xD0180000
47 #endif
48 #define CONFIG_SYS_I2C_SPEED			400000
49 #define CONFIG_SYS_I2C_SLAVE			0x02
50 
51 #define CONFIG_I2C_CHIPADDRESS			0x50
52 
53 /* Timer, HZ specific defines */
54 
55 /* Flash configuration */
56 #if defined(CONFIG_FLASH_PNOR)
57 #define CONFIG_SPEAR_EMI
58 #else
59 #define CONFIG_ST_SMI
60 #endif
61 
62 #if defined(CONFIG_ST_SMI)
63 
64 #define CONFIG_SYS_MAX_FLASH_BANKS		2
65 #define CONFIG_SYS_FLASH_BASE			0xF8000000
66 #define CONFIG_SYS_CS1_FLASH_BASE		0xF9000000
67 #define CONFIG_SYS_FLASH_BANK_SIZE		0x01000000
68 #define CONFIG_SYS_FLASH_ADDR_BASE		{CONFIG_SYS_FLASH_BASE, \
69 						CONFIG_SYS_CS1_FLASH_BASE}
70 #define CONFIG_SYS_MAX_FLASH_SECT		128
71 
72 #define CONFIG_SYS_FLASH_ERASE_TOUT		(3 * CONFIG_SYS_HZ)
73 #define CONFIG_SYS_FLASH_WRITE_TOUT		(3 * CONFIG_SYS_HZ)
74 
75 #endif
76 
77 /*
78  * Serial Configuration (PL011)
79  * CONFIG_PL01x_PORTS is defined in specific files
80  */
81 #define CONFIG_PL011_SERIAL
82 #define CONFIG_PL011_CLOCK			(48 * 1000 * 1000)
83 #define CONFIG_CONS_INDEX			0
84 #define CONFIG_BAUDRATE				115200
85 #define CONFIG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, \
86 						57600, 115200 }
87 
88 #define CONFIG_SYS_LOADS_BAUD_CHANGE
89 
90 /* NAND FLASH Configuration */
91 #define CONFIG_SYS_NAND_SELF_INIT
92 #define CONFIG_MTD_DEVICE
93 #define CONFIG_MTD_PARTITIONS
94 #define CONFIG_NAND_FSMC
95 #define CONFIG_SYS_MAX_NAND_DEVICE		1
96 #define CONFIG_SYS_NAND_ONFI_DETECTION
97 
98 /*
99  * Command support defines
100  */
101 #define CONFIG_CMD_NAND
102 #define CONFIG_CMD_ENV
103 #define CONFIG_CMD_SAVES
104 
105 /*
106  * Default Environment Varible definitions
107  */
108 #if defined(CONFIG_SPEAR_USBTTY)
109 #define CONFIG_BOOTDELAY			-1
110 #else
111 #define CONFIG_BOOTDELAY			1
112 #endif
113 
114 #define CONFIG_ENV_OVERWRITE
115 
116 /*
117  * U-Boot Environment placing definitions.
118  */
119 #if defined(CONFIG_ENV_IS_IN_FLASH)
120 #ifdef CONFIG_ST_SMI
121 /*
122  * Environment is in serial NOR flash
123  */
124 #define CONFIG_SYS_MONITOR_LEN			0x00040000
125 #define CONFIG_ENV_SECT_SIZE			0x00010000
126 #define CONFIG_FSMTDBLK				"/dev/mtdblock3 "
127 
128 #define CONFIG_BOOTCOMMAND			"bootm 0xf8050000"
129 
130 #elif defined(CONFIG_SPEAR_EMI)
131 /*
132  * Environment is in parallel NOR flash
133  */
134 #define CONFIG_SYS_MONITOR_LEN			0x00060000
135 #define CONFIG_ENV_SECT_SIZE			0x00020000
136 #define CONFIG_FSMTDBLK				"/dev/mtdblock3 "
137 
138 #define CONFIG_BOOTCOMMAND			"cp.b 0x50080000 0x1600000 " \
139 						"0x4C0000; bootm 0x1600000"
140 #endif
141 
142 #define CONFIG_ENV_ADDR				(CONFIG_SYS_FLASH_BASE + \
143 						CONFIG_SYS_MONITOR_LEN)
144 #elif defined(CONFIG_ENV_IS_IN_NAND)
145 /*
146  * Environment is in NAND
147  */
148 
149 #define CONFIG_ENV_OFFSET			0x60000
150 #define CONFIG_ENV_RANGE			0x10000
151 #define CONFIG_FSMTDBLK				"/dev/mtdblock7 "
152 
153 #define CONFIG_BOOTCOMMAND			"nand read.jffs2 0x1600000 " \
154 						"0x80000 0x4C0000; " \
155 						"bootm 0x1600000"
156 #endif
157 
158 #define CONFIG_BOOTARGS				"console=ttyAMA0,115200 " \
159 						"mem=128M " \
160 						"root="CONFIG_FSMTDBLK \
161 						"rootfstype=jffs2"
162 
163 #define CONFIG_NFSBOOTCOMMAND						\
164 	"bootp; "							\
165 	"setenv bootargs root=/dev/nfs rw "				\
166 	"nfsroot=$(serverip):$(rootpath) "				\
167 	"ip=$(ipaddr):$(serverip):$(gatewayip):"			\
168 			"$(netmask):$(hostname):$(netdev):off "		\
169 			"console=ttyAMA0,115200 $(othbootargs);"	\
170 	"bootm; "
171 
172 #define CONFIG_RAMBOOTCOMMAND						\
173 	"setenv bootargs root=/dev/ram rw "				\
174 		"console=ttyAMA0,115200 $(othbootargs);"		\
175 	CONFIG_BOOTCOMMAND
176 
177 #define CONFIG_ENV_SIZE				0x02000
178 #define CONFIG_SYS_MONITOR_BASE			CONFIG_SYS_TEXT_BASE
179 
180 /* Miscellaneous configurable options */
181 #define CONFIG_ARCH_CPU_INIT
182 #define CONFIG_BOARD_EARLY_INIT_F
183 #define CONFIG_DISPLAY_CPUINFO
184 #define CONFIG_BOOT_PARAMS_ADDR			0x00000100
185 #define CONFIG_CMDLINE_TAG
186 #define CONFIG_SETUP_MEMORY_TAGS
187 #define CONFIG_MISC_INIT_R
188 #define CONFIG_ZERO_BOOTDELAY_CHECK
189 
190 #define CONFIG_SYS_MEMTEST_START		0x00800000
191 #define CONFIG_SYS_MEMTEST_END			0x04000000
192 #define CONFIG_SYS_MALLOC_LEN			(1024*1024)
193 #define CONFIG_IDENT_STRING			"-SPEAr"
194 #define CONFIG_SYS_LONGHELP
195 #define CONFIG_CMDLINE_EDITING
196 #define CONFIG_SYS_CBSIZE			256
197 #define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + \
198 						sizeof(CONFIG_SYS_PROMPT) + 16)
199 #define CONFIG_SYS_MAXARGS			16
200 #define CONFIG_SYS_BARGSIZE			CONFIG_SYS_CBSIZE
201 #define CONFIG_SYS_LOAD_ADDR			0x00800000
202 #define CONFIG_SYS_CONSOLE_INFO_QUIET
203 
204 #define CONFIG_SYS_FLASH_EMPTY_INFO
205 
206 /* Physical Memory Map */
207 #define CONFIG_NR_DRAM_BANKS			1
208 #define PHYS_SDRAM_1				0x00000000
209 #define PHYS_SDRAM_1_MAXSIZE			0x40000000
210 
211 #define CONFIG_SYS_SDRAM_BASE			PHYS_SDRAM_1
212 #define CONFIG_SYS_INIT_RAM_ADDR		0xD2800000
213 #define CONFIG_SYS_INIT_RAM_SIZE		0x2000
214 
215 #define CONFIG_SYS_INIT_SP_OFFSET		\
216 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
217 
218 #define CONFIG_SYS_INIT_SP_ADDR			\
219 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
220 
221 #endif
222