1 /* 2 * (C) Copyright 2008 3 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. 4 * 5 * Wolfgang Denk <wd@denx.de> 6 * Copyright 2004 Freescale Semiconductor. 7 * (C) Copyright 2002,2003 Motorola,Inc. 8 * Xianghua Xiao <X.Xiao@motorola.com> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 /* 14 * Socrates 15 */ 16 17 #ifndef __CONFIG_H 18 #define __CONFIG_H 19 20 /* High Level Configuration Options */ 21 #define CONFIG_BOOKE 1 /* BOOKE */ 22 #define CONFIG_E500 1 /* BOOKE e500 family */ 23 #define CONFIG_MPC8544 1 24 #define CONFIG_SOCRATES 1 25 26 #define CONFIG_SYS_TEXT_BASE 0xfff80000 27 28 #define CONFIG_PCI_INDIRECT_BRIDGE 29 30 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 31 32 #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ 33 #define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */ 34 35 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 36 37 /* 38 * Only possible on E500 Version 2 or newer cores. 39 */ 40 #define CONFIG_ENABLE_36BIT_PHYS 1 41 42 /* 43 * sysclk for MPC85xx 44 * 45 * Two valid values are: 46 * 33000000 47 * 66000000 48 * 49 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 50 * is likely the desired value here, so that is now the default. 51 * The board, however, can run at 66MHz. In any event, this value 52 * must match the settings of some switches. Details can be found 53 * in the README.mpc85xxads. 54 */ 55 56 #ifndef CONFIG_SYS_CLK_FREQ 57 #define CONFIG_SYS_CLK_FREQ 66666666 58 #endif 59 60 /* 61 * These can be toggled for performance analysis, otherwise use default. 62 */ 63 #define CONFIG_L2_CACHE /* toggle L2 cache */ 64 #define CONFIG_BTB /* toggle branch predition */ 65 66 #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ 67 68 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 69 #define CONFIG_SYS_MEMTEST_START 0x00400000 70 #define CONFIG_SYS_MEMTEST_END 0x00C00000 71 72 #define CONFIG_SYS_CCSRBAR 0xE0000000 73 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 74 75 /* DDR Setup */ 76 #define CONFIG_SYS_FSL_DDR2 77 #undef CONFIG_FSL_DDR_INTERACTIVE 78 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 79 #define CONFIG_DDR_SPD 80 81 #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 82 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 83 84 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 85 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 86 #define CONFIG_VERY_BIG_RAM 87 88 #define CONFIG_NUM_DDR_CONTROLLERS 1 89 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 90 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 91 92 /* I2C addresses of SPD EEPROMs */ 93 #define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */ 94 95 #define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ 96 97 /* Hardcoded values, to use instead of SPD */ 98 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f 99 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 100 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 101 #define CONFIG_SYS_DDR_TIMING_1 0x3935D322 102 #define CONFIG_SYS_DDR_TIMING_2 0x14904CC8 103 #define CONFIG_SYS_DDR_MODE 0x00480432 104 #define CONFIG_SYS_DDR_INTERVAL 0x030C0100 105 #define CONFIG_SYS_DDR_CONFIG_2 0x04400000 106 #define CONFIG_SYS_DDR_CONFIG 0xC3008000 107 #define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000 108 #define CONFIG_SYS_SDRAM_SIZE 256 /* in Megs */ 109 110 /* 111 * Flash on the LocalBus 112 */ 113 #define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ 114 115 #define CONFIG_SYS_FLASH0 0xFE000000 116 #define CONFIG_SYS_FLASH1 0xFC000000 117 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 } 118 119 #define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */ 120 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */ 121 122 #define CONFIG_SYS_BR0_PRELIM 0xfe001001 /* port size 16bit */ 123 #define CONFIG_SYS_OR0_PRELIM 0xfe000030 /* 32MB Flash */ 124 #define CONFIG_SYS_BR1_PRELIM 0xfc001001 /* port size 16bit */ 125 #define CONFIG_SYS_OR1_PRELIM 0xfe000030 /* 32MB Flash */ 126 127 #define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */ 128 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/ 129 130 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 131 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ 132 #undef CONFIG_SYS_FLASH_CHECKSUM 133 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 134 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 135 136 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 137 138 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 139 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 140 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 141 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ 142 143 #define CONFIG_SYS_INIT_RAM_LOCK 1 144 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 145 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/ 146 147 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 148 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 149 150 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384KiB for Mon */ 151 #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */ 152 153 /* FPGA and NAND */ 154 #define CONFIG_SYS_FPGA_BASE 0xc0000000 155 #define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */ 156 #define CONFIG_SYS_HMI_BASE 0xc0010000 157 #define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */ 158 #define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */ 159 160 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70) 161 #define CONFIG_SYS_MAX_NAND_DEVICE 1 162 #define CONFIG_CMD_NAND 163 164 /* LIME GDC */ 165 #define CONFIG_SYS_LIME_BASE 0xc8000000 166 #define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */ 167 #define CONFIG_SYS_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */ 168 #define CONFIG_SYS_OR2_PRELIM 0xfc000000 /* 64 MB */ 169 170 #define CONFIG_VIDEO_MB862xx 171 #define CONFIG_VIDEO_MB862xx_ACCEL 172 #define CONFIG_VIDEO_LOGO 173 #define CONFIG_VIDEO_BMP_LOGO 174 #define VIDEO_FB_16BPP_PIXEL_SWAP 175 #define VIDEO_FB_16BPP_WORD_SWAP 176 #define CONFIG_SPLASH_SCREEN 177 #define CONFIG_VIDEO_BMP_GZIP 178 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */ 179 180 /* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */ 181 #define CONFIG_SYS_MB862xx_CCF 0x10000 182 /* SDRAM parameter */ 183 #define CONFIG_SYS_MB862xx_MMR 0x4157BA63 184 185 /* Serial Port */ 186 187 #define CONFIG_CONS_INDEX 1 188 #define CONFIG_SYS_NS16550_SERIAL 189 #define CONFIG_SYS_NS16550_REG_SIZE 1 190 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 191 192 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 193 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 194 195 #define CONFIG_BAUDRATE 115200 196 197 #define CONFIG_SYS_BAUDRATE_TABLE \ 198 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 199 200 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 201 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ 202 203 /* 204 * I2C 205 */ 206 #define CONFIG_SYS_I2C 207 #define CONFIG_SYS_I2C_FSL 208 #define CONFIG_SYS_FSL_I2C_SPEED 102124 209 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 210 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 211 #define CONFIG_SYS_FSL_I2C2_SPEED 102124 212 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 213 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 214 215 /* I2C RTC */ 216 #define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */ 217 #define CONFIG_SYS_I2C_RTC_ADDR 0x32 /* at address 0x32 */ 218 219 /* I2C W83782G HW-Monitoring IC */ 220 #define CONFIG_SYS_I2C_W83782G_ADDR 0x28 /* W83782G address */ 221 222 /* I2C temp sensor */ 223 /* Socrates uses Maxim's DS75, which is compatible with LM75 */ 224 #define CONFIG_DTT_LM75 1 225 #define CONFIG_DTT_SENSORS {4} /* Sensor addresses */ 226 #define CONFIG_SYS_DTT_MAX_TEMP 125 227 #define CONFIG_SYS_DTT_LOW_TEMP -55 228 #define CONFIG_SYS_DTT_HYSTERESIS 3 229 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 230 231 /* 232 * General PCI 233 * Memory space is mapped 1-1. 234 */ 235 #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ 236 237 /* PCI is clocked by the external source at 33 MHz */ 238 #define CONFIG_PCI_CLK_FREQ 33000000 239 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 240 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 241 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 242 #define CONFIG_SYS_PCI1_IO_BASE 0xE2000000 243 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE 244 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ 245 246 #if defined(CONFIG_PCI) 247 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 248 #endif /* CONFIG_PCI */ 249 250 #define CONFIG_MII 1 /* MII PHY management */ 251 #define CONFIG_TSEC1 1 252 #define CONFIG_TSEC1_NAME "TSEC0" 253 #define CONFIG_TSEC3 1 254 #define CONFIG_TSEC3_NAME "TSEC1" 255 #undef CONFIG_MPC85XX_FEC 256 257 #define TSEC1_PHY_ADDR 0 258 #define TSEC3_PHY_ADDR 1 259 260 #define TSEC1_PHYIDX 0 261 #define TSEC3_PHYIDX 0 262 #define TSEC1_FLAGS TSEC_GIGABIT 263 #define TSEC3_FLAGS TSEC_GIGABIT 264 265 /* Options are: TSEC[0,1] */ 266 #define CONFIG_ETHPRIME "TSEC0" 267 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 268 269 #define CONFIG_HAS_ETH0 270 #define CONFIG_HAS_ETH1 271 272 /* 273 * Environment 274 */ 275 #define CONFIG_ENV_IS_IN_FLASH 1 276 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 277 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 278 #define CONFIG_ENV_SIZE 0x4000 279 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) 280 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 281 282 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 283 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 284 285 #define CONFIG_TIMESTAMP /* Print image info with ts */ 286 287 /* 288 * BOOTP options 289 */ 290 #define CONFIG_BOOTP_BOOTFILESIZE 291 #define CONFIG_BOOTP_BOOTPATH 292 #define CONFIG_BOOTP_GATEWAY 293 #define CONFIG_BOOTP_HOSTNAME 294 295 /* 296 * Command line configuration. 297 */ 298 #define CONFIG_CMD_BMP 299 #define CONFIG_CMD_DATE 300 #define CONFIG_CMD_DTT 301 #undef CONFIG_CMD_EEPROM 302 #define CONFIG_CMD_SDRAM 303 #define CONFIG_CMD_REGINFO 304 305 #if defined(CONFIG_PCI) 306 #define CONFIG_CMD_PCI 307 #endif 308 309 #undef CONFIG_WATCHDOG /* watchdog disabled */ 310 311 /* 312 * Miscellaneous configurable options 313 */ 314 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 315 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 316 317 #if defined(CONFIG_CMD_KGDB) 318 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 319 #else 320 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 321 #endif 322 323 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buf Size */ 324 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 325 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 326 327 /* 328 * For booting Linux, the board info and command line data 329 * have to be in the first 8 MB of memory, since this is 330 * the maximum mapped by the Linux kernel during initialization. 331 */ 332 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 333 334 #if defined(CONFIG_CMD_KGDB) 335 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/ 336 #endif 337 338 #define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/ 339 340 341 #define CONFIG_PREBOOT "echo;" \ 342 "echo Welcome on the ABB Socrates Board;" \ 343 "echo" 344 345 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 346 347 #define CONFIG_EXTRA_ENV_SETTINGS \ 348 "netdev=eth0\0" \ 349 "consdev=ttyS0\0" \ 350 "uboot_file=/home/tftp/syscon3/u-boot.bin\0" \ 351 "bootfile=/home/tftp/syscon3/uImage\0" \ 352 "fdt_file=/home/tftp/syscon3/socrates.dtb\0" \ 353 "initrd_file=/home/tftp/syscon3/uinitrd.gz\0" \ 354 "uboot_addr=FFFA0000\0" \ 355 "kernel_addr=FE000000\0" \ 356 "fdt_addr=FE1E0000\0" \ 357 "ramdisk_addr=FE200000\0" \ 358 "fdt_addr_r=B00000\0" \ 359 "kernel_addr_r=200000\0" \ 360 "ramdisk_addr_r=400000\0" \ 361 "rootpath=/opt/eldk/ppc_85xxDP\0" \ 362 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 363 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 364 "nfsroot=$serverip:$rootpath\0" \ 365 "addcons=setenv bootargs $bootargs " \ 366 "console=$consdev,$baudrate\0" \ 367 "addip=setenv bootargs $bootargs " \ 368 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ 369 ":$hostname:$netdev:off panic=1\0" \ 370 "boot_nor=run ramargs addcons;" \ 371 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 372 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 373 "tftp ${fdt_addr_r} ${fdt_file}; " \ 374 "run nfsargs addip addcons;" \ 375 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 376 "update_uboot=tftp 100000 ${uboot_file};" \ 377 "protect off fffa0000 ffffffff;" \ 378 "era fffa0000 ffffffff;" \ 379 "cp.b 100000 fffa0000 ${filesize};" \ 380 "setenv filesize;saveenv\0" \ 381 "update_kernel=tftp 100000 ${bootfile};" \ 382 "era fe000000 fe1dffff;" \ 383 "cp.b 100000 fe000000 ${filesize};" \ 384 "setenv filesize;saveenv\0" \ 385 "update_fdt=tftp 100000 ${fdt_file};" \ 386 "era fe1e0000 fe1fffff;" \ 387 "cp.b 100000 fe1e0000 ${filesize};" \ 388 "setenv filesize;saveenv\0" \ 389 "update_initrd=tftp 100000 ${initrd_file};" \ 390 "era fe200000 fe9fffff;" \ 391 "cp.b 100000 fe200000 ${filesize};" \ 392 "setenv filesize;saveenv\0" \ 393 "clean_data=era fea00000 fff5ffff\0" \ 394 "usbargs=setenv bootargs root=/dev/sda1 rw\0" \ 395 "load_usb=usb start;" \ 396 "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \ 397 "boot_usb=run load_usb usbargs addcons;" \ 398 "bootm ${kernel_addr_r} - ${fdt_addr};" \ 399 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 400 "" 401 #define CONFIG_BOOTCOMMAND "run boot_nor" 402 403 /* pass open firmware flat tree */ 404 405 /* USB support */ 406 #define CONFIG_USB_OHCI_NEW 1 407 #define CONFIG_PCI_OHCI 1 408 #define CONFIG_PCI_OHCI_DEVNO 3 /* Number in PCI list */ 409 #define CONFIG_PCI_EHCI_DEVNO (CONFIG_PCI_OHCI_DEVNO / 2) 410 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 411 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" 412 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 413 #define CONFIG_DOS_PARTITION 1 414 415 #endif /* __CONFIG_H */ 416