1 /* 2 * (C) Copyright 2008 3 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. 4 * 5 * Wolfgang Denk <wd@denx.de> 6 * Copyright 2004 Freescale Semiconductor. 7 * (C) Copyright 2002,2003 Motorola,Inc. 8 * Xianghua Xiao <X.Xiao@motorola.com> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 /* 14 * Socrates 15 */ 16 17 #ifndef __CONFIG_H 18 #define __CONFIG_H 19 20 /* High Level Configuration Options */ 21 #define CONFIG_SOCRATES 1 22 23 #define CONFIG_PCI_INDIRECT_BRIDGE 24 25 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 26 27 #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ 28 #define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */ 29 30 /* 31 * Only possible on E500 Version 2 or newer cores. 32 */ 33 #define CONFIG_ENABLE_36BIT_PHYS 1 34 35 /* 36 * sysclk for MPC85xx 37 * 38 * Two valid values are: 39 * 33000000 40 * 66000000 41 * 42 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 43 * is likely the desired value here, so that is now the default. 44 * The board, however, can run at 66MHz. In any event, this value 45 * must match the settings of some switches. Details can be found 46 * in the README.mpc85xxads. 47 */ 48 49 #ifndef CONFIG_SYS_CLK_FREQ 50 #define CONFIG_SYS_CLK_FREQ 66666666 51 #endif 52 53 /* 54 * These can be toggled for performance analysis, otherwise use default. 55 */ 56 #define CONFIG_L2_CACHE /* toggle L2 cache */ 57 #define CONFIG_BTB /* toggle branch predition */ 58 59 #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ 60 61 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 62 #define CONFIG_SYS_MEMTEST_START 0x00400000 63 #define CONFIG_SYS_MEMTEST_END 0x00C00000 64 65 #define CONFIG_SYS_CCSRBAR 0xE0000000 66 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 67 68 /* DDR Setup */ 69 #undef CONFIG_FSL_DDR_INTERACTIVE 70 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 71 #define CONFIG_DDR_SPD 72 73 #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 74 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 75 76 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 77 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 78 #define CONFIG_VERY_BIG_RAM 79 80 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 81 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 82 83 /* I2C addresses of SPD EEPROMs */ 84 #define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */ 85 86 #define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ 87 88 /* Hardcoded values, to use instead of SPD */ 89 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f 90 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 91 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 92 #define CONFIG_SYS_DDR_TIMING_1 0x3935D322 93 #define CONFIG_SYS_DDR_TIMING_2 0x14904CC8 94 #define CONFIG_SYS_DDR_MODE 0x00480432 95 #define CONFIG_SYS_DDR_INTERVAL 0x030C0100 96 #define CONFIG_SYS_DDR_CONFIG_2 0x04400000 97 #define CONFIG_SYS_DDR_CONFIG 0xC3008000 98 #define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000 99 #define CONFIG_SYS_SDRAM_SIZE 256 /* in Megs */ 100 101 /* 102 * Flash on the LocalBus 103 */ 104 #define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ 105 106 #define CONFIG_SYS_FLASH0 0xFE000000 107 #define CONFIG_SYS_FLASH1 0xFC000000 108 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 } 109 110 #define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */ 111 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */ 112 113 #define CONFIG_SYS_BR0_PRELIM 0xfe001001 /* port size 16bit */ 114 #define CONFIG_SYS_OR0_PRELIM 0xfe000030 /* 32MB Flash */ 115 #define CONFIG_SYS_BR1_PRELIM 0xfc001001 /* port size 16bit */ 116 #define CONFIG_SYS_OR1_PRELIM 0xfe000030 /* 32MB Flash */ 117 118 #define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */ 119 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/ 120 121 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 122 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ 123 #undef CONFIG_SYS_FLASH_CHECKSUM 124 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 125 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 126 127 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 128 129 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 130 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 131 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 132 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ 133 134 #define CONFIG_SYS_INIT_RAM_LOCK 1 135 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 136 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/ 137 138 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 139 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 140 141 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384KiB for Mon */ 142 #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */ 143 144 /* FPGA and NAND */ 145 #define CONFIG_SYS_FPGA_BASE 0xc0000000 146 #define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */ 147 #define CONFIG_SYS_HMI_BASE 0xc0010000 148 #define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */ 149 #define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */ 150 151 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70) 152 #define CONFIG_SYS_MAX_NAND_DEVICE 1 153 154 /* LIME GDC */ 155 #define CONFIG_SYS_LIME_BASE 0xc8000000 156 #define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */ 157 #define CONFIG_SYS_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */ 158 #define CONFIG_SYS_OR2_PRELIM 0xfc000000 /* 64 MB */ 159 160 #define CONFIG_VIDEO_MB862xx 161 #define CONFIG_VIDEO_MB862xx_ACCEL 162 #define CONFIG_VIDEO_LOGO 163 #define CONFIG_VIDEO_BMP_LOGO 164 #define VIDEO_FB_16BPP_PIXEL_SWAP 165 #define VIDEO_FB_16BPP_WORD_SWAP 166 #define CONFIG_SPLASH_SCREEN 167 #define CONFIG_VIDEO_BMP_GZIP 168 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */ 169 170 /* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */ 171 #define CONFIG_SYS_MB862xx_CCF 0x10000 172 /* SDRAM parameter */ 173 #define CONFIG_SYS_MB862xx_MMR 0x4157BA63 174 175 /* Serial Port */ 176 177 #define CONFIG_SYS_NS16550_SERIAL 178 #define CONFIG_SYS_NS16550_REG_SIZE 1 179 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 180 181 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 182 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 183 184 #define CONFIG_SYS_BAUDRATE_TABLE \ 185 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 186 187 /* 188 * I2C 189 */ 190 #define CONFIG_SYS_I2C 191 #define CONFIG_SYS_I2C_FSL 192 #define CONFIG_SYS_FSL_I2C_SPEED 102124 193 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 194 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 195 #define CONFIG_SYS_FSL_I2C2_SPEED 102124 196 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 197 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 198 199 /* I2C RTC */ 200 #define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */ 201 #define CONFIG_SYS_I2C_RTC_ADDR 0x32 /* at address 0x32 */ 202 203 /* I2C W83782G HW-Monitoring IC */ 204 #define CONFIG_SYS_I2C_W83782G_ADDR 0x28 /* W83782G address */ 205 206 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 207 208 /* 209 * General PCI 210 * Memory space is mapped 1-1. 211 */ 212 #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ 213 214 /* PCI is clocked by the external source at 33 MHz */ 215 #define CONFIG_PCI_CLK_FREQ 33000000 216 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 217 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 218 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 219 #define CONFIG_SYS_PCI1_IO_BASE 0xE2000000 220 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE 221 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ 222 223 #if defined(CONFIG_PCI) 224 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 225 #endif /* CONFIG_PCI */ 226 227 #define CONFIG_MII 1 /* MII PHY management */ 228 #define CONFIG_TSEC1 1 229 #define CONFIG_TSEC1_NAME "TSEC0" 230 #define CONFIG_TSEC3 1 231 #define CONFIG_TSEC3_NAME "TSEC1" 232 #undef CONFIG_MPC85XX_FEC 233 234 #define TSEC1_PHY_ADDR 0 235 #define TSEC3_PHY_ADDR 1 236 237 #define TSEC1_PHYIDX 0 238 #define TSEC3_PHYIDX 0 239 #define TSEC1_FLAGS TSEC_GIGABIT 240 #define TSEC3_FLAGS TSEC_GIGABIT 241 242 /* Options are: TSEC[0,1] */ 243 #define CONFIG_ETHPRIME "TSEC0" 244 245 #define CONFIG_HAS_ETH0 246 #define CONFIG_HAS_ETH1 247 248 /* 249 * Environment 250 */ 251 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 252 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 253 #define CONFIG_ENV_SIZE 0x4000 254 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) 255 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 256 257 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 258 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 259 260 #define CONFIG_TIMESTAMP /* Print image info with ts */ 261 262 /* 263 * BOOTP options 264 */ 265 #define CONFIG_BOOTP_BOOTFILESIZE 266 267 #undef CONFIG_WATCHDOG /* watchdog disabled */ 268 269 /* 270 * Miscellaneous configurable options 271 */ 272 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 273 274 /* 275 * For booting Linux, the board info and command line data 276 * have to be in the first 8 MB of memory, since this is 277 * the maximum mapped by the Linux kernel during initialization. 278 */ 279 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 280 281 #if defined(CONFIG_CMD_KGDB) 282 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/ 283 #endif 284 285 #define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/ 286 287 288 #define CONFIG_PREBOOT "echo;" \ 289 "echo Welcome on the ABB Socrates Board;" \ 290 "echo" 291 292 #define CONFIG_EXTRA_ENV_SETTINGS \ 293 "netdev=eth0\0" \ 294 "consdev=ttyS0\0" \ 295 "uboot_file=/home/tftp/syscon3/u-boot.bin\0" \ 296 "bootfile=/home/tftp/syscon3/uImage\0" \ 297 "fdt_file=/home/tftp/syscon3/socrates.dtb\0" \ 298 "initrd_file=/home/tftp/syscon3/uinitrd.gz\0" \ 299 "uboot_addr=FFFA0000\0" \ 300 "kernel_addr=FE000000\0" \ 301 "fdt_addr=FE1E0000\0" \ 302 "ramdisk_addr=FE200000\0" \ 303 "fdt_addr_r=B00000\0" \ 304 "kernel_addr_r=200000\0" \ 305 "ramdisk_addr_r=400000\0" \ 306 "rootpath=/opt/eldk/ppc_85xxDP\0" \ 307 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 308 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 309 "nfsroot=$serverip:$rootpath\0" \ 310 "addcons=setenv bootargs $bootargs " \ 311 "console=$consdev,$baudrate\0" \ 312 "addip=setenv bootargs $bootargs " \ 313 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ 314 ":$hostname:$netdev:off panic=1\0" \ 315 "boot_nor=run ramargs addcons;" \ 316 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 317 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 318 "tftp ${fdt_addr_r} ${fdt_file}; " \ 319 "run nfsargs addip addcons;" \ 320 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 321 "update_uboot=tftp 100000 ${uboot_file};" \ 322 "protect off fffa0000 ffffffff;" \ 323 "era fffa0000 ffffffff;" \ 324 "cp.b 100000 fffa0000 ${filesize};" \ 325 "setenv filesize;saveenv\0" \ 326 "update_kernel=tftp 100000 ${bootfile};" \ 327 "era fe000000 fe1dffff;" \ 328 "cp.b 100000 fe000000 ${filesize};" \ 329 "setenv filesize;saveenv\0" \ 330 "update_fdt=tftp 100000 ${fdt_file};" \ 331 "era fe1e0000 fe1fffff;" \ 332 "cp.b 100000 fe1e0000 ${filesize};" \ 333 "setenv filesize;saveenv\0" \ 334 "update_initrd=tftp 100000 ${initrd_file};" \ 335 "era fe200000 fe9fffff;" \ 336 "cp.b 100000 fe200000 ${filesize};" \ 337 "setenv filesize;saveenv\0" \ 338 "clean_data=era fea00000 fff5ffff\0" \ 339 "usbargs=setenv bootargs root=/dev/sda1 rw\0" \ 340 "load_usb=usb start;" \ 341 "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \ 342 "boot_usb=run load_usb usbargs addcons;" \ 343 "bootm ${kernel_addr_r} - ${fdt_addr};" \ 344 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 345 "" 346 #define CONFIG_BOOTCOMMAND "run boot_nor" 347 348 /* pass open firmware flat tree */ 349 350 /* USB support */ 351 #define CONFIG_USB_OHCI_NEW 1 352 #define CONFIG_PCI_OHCI 1 353 #define CONFIG_PCI_OHCI_DEVNO 3 /* Number in PCI list */ 354 #define CONFIG_PCI_EHCI_DEVNO (CONFIG_PCI_OHCI_DEVNO / 2) 355 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 356 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" 357 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 358 359 #endif /* __CONFIG_H */ 360