xref: /openbmc/u-boot/include/configs/socrates.h (revision 7d9b5bae)
1 /*
2  * (C) Copyright 2008
3  * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
4  *
5  * Wolfgang Denk <wd@denx.de>
6  * Copyright 2004 Freescale Semiconductor.
7  * (C) Copyright 2002,2003 Motorola,Inc.
8  * Xianghua Xiao <X.Xiao@motorola.com>
9  *
10  * See file CREDITS for list of people who contributed to this
11  * project.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License as
15  * published by the Free Software Foundation; either version 2 of
16  * the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software
25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26  * MA 02111-1307 USA
27  */
28 
29 /*
30  * Socrates
31  */
32 
33 #ifndef __CONFIG_H
34 #define __CONFIG_H
35 
36 /* High Level Configuration Options */
37 #define CONFIG_BOOKE		1	/* BOOKE			*/
38 #define CONFIG_E500		1	/* BOOKE e500 family		*/
39 #define CONFIG_MPC85xx		1	/* MPC8540/60/55/41		*/
40 #define CONFIG_MPC8544		1
41 #define CONFIG_SOCRATES		1
42 
43 #define CONFIG_PCI
44 
45 #define CONFIG_TSEC_ENET		/* tsec ethernet support	*/
46 
47 #define CONFIG_MISC_INIT_R	1	/* Call misc_init_r		*/
48 #define CONFIG_BOARD_EARLY_INIT_R 1	/* Call board_early_init_r	*/
49 
50 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
51 
52 /*
53  * Only possible on E500 Version 2 or newer cores.
54  */
55 #define CONFIG_ENABLE_36BIT_PHYS	1
56 
57 /*
58  * sysclk for MPC85xx
59  *
60  * Two valid values are:
61  *    33000000
62  *    66000000
63  *
64  * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
65  * is likely the desired value here, so that is now the default.
66  * The board, however, can run at 66MHz.  In any event, this value
67  * must match the settings of some switches.  Details can be found
68  * in the README.mpc85xxads.
69  */
70 
71 #ifndef CONFIG_SYS_CLK_FREQ
72 #define CONFIG_SYS_CLK_FREQ	66666666
73 #endif
74 
75 /*
76  * These can be toggled for performance analysis, otherwise use default.
77  */
78 #define CONFIG_L2_CACHE			/* toggle L2 cache		*/
79 #define CONFIG_BTB			/* toggle branch predition	*/
80 #define CONFIG_ADDR_STREAMING		/* toggle addr streaming	*/
81 
82 #define CFG_INIT_DBCR DBCR_IDM		/* Enable Debug Exceptions	*/
83 
84 #undef	CFG_DRAM_TEST			/* memory test, takes time	*/
85 #define CFG_MEMTEST_START	0x00000000
86 #define CFG_MEMTEST_END		0x10000000
87 
88 /*
89  * Base addresses -- Note these are effective addresses where the
90  * actual resources get mapped (not physical addresses)
91  */
92 #define CFG_CCSRBAR_DEFAULT	0xFF700000	/* CCSRBAR Default	*/
93 #define CFG_CCSRBAR		0xE0000000	/* relocated CCSRBAR	*/
94 #define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
95 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/
96 
97 /* DDR Setup */
98 #define CONFIG_FSL_DDR2
99 #undef CONFIG_FSL_DDR_INTERACTIVE
100 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
101 #define CONFIG_DDR_SPD
102 
103 #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
104 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
105 
106 #define CFG_DDR_SDRAM_BASE	0x00000000
107 #define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
108 #define CONFIG_VERY_BIG_RAM
109 
110 #define CONFIG_NUM_DDR_CONTROLLERS	1
111 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
112 #define CONFIG_CHIP_SELECTS_PER_CTRL	2
113 
114 /* I2C addresses of SPD EEPROMs */
115 #define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
116 
117 #define CONFIG_DDR_DEFAULT_CL	30		/* CAS latency 3	*/
118 
119 /* Hardcoded values, to use instead of SPD */
120 #define CFG_DDR_CS0_BNDS		0x0000000f
121 #define CFG_DDR_CS0_CONFIG		0x80010102
122 #define CFG_DDR_TIMING_0		0x00260802
123 #define CFG_DDR_TIMING_1		0x3935D322
124 #define CFG_DDR_TIMING_2		0x14904CC8
125 #define CFG_DDR_MODE			0x00480432
126 #define CFG_DDR_INTERVAL		0x030C0100
127 #define CFG_DDR_CONFIG_2		0x04400000
128 #define CFG_DDR_CONFIG			0xC3008000
129 #define CFG_DDR_CLK_CONTROL		0x03800000
130 #define CFG_SDRAM_SIZE			256 /* in Megs */
131 
132 /*
133  * Flash on the LocalBus
134  */
135 #define CFG_LBC_CACHE_BASE	0xf0000000	/* Localbus cacheable	 */
136 
137 #define CFG_FLASH0		0xFE000000
138 #define CFG_FLASH1		0xFC000000
139 #define CFG_FLASH_BANKS_LIST	{ CFG_FLASH1, CFG_FLASH0 }
140 
141 #define CFG_LBC_FLASH_BASE	CFG_FLASH1	/* Localbus flash start	*/
142 #define CFG_FLASH_BASE		CFG_LBC_FLASH_BASE /* start of FLASH	*/
143 
144 #define CFG_BR0_PRELIM		0xfe001001	/* port size 16bit	*/
145 #define CFG_OR0_PRELIM		0xfe000030	/* 32MB Flash		*/
146 #define CFG_BR1_PRELIM		0xfc001001	/* port size 16bit	*/
147 #define CFG_OR1_PRELIM		0xfe000030	/* 32MB Flash		*/
148 
149 #define CFG_FLASH_CFI				/* flash is CFI compat.	*/
150 #define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver*/
151 
152 #define CFG_MAX_FLASH_BANKS	2		/* number of banks	*/
153 #define CFG_MAX_FLASH_SECT	256		/* sectors per device	*/
154 #undef	CFG_FLASH_CHECKSUM
155 #define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms)	*/
156 #define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms)	*/
157 
158 #define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor	*/
159 
160 #define CFG_LBC_LCRR		0x00030004    /* LB clock ratio reg	*/
161 #define CFG_LBC_LBCR		0x00000000    /* LB config reg		*/
162 #define CFG_LBC_LSRT		0x20000000    /* LB sdram refresh timer	*/
163 #define CFG_LBC_MRTPR		0x20000000    /* LB refresh timer presc.*/
164 
165 #define CONFIG_L1_INIT_RAM
166 #define CFG_INIT_RAM_LOCK	1
167 #define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address	*/
168 #define CFG_INIT_RAM_END	0x4000		/* End used area in RAM	*/
169 
170 #define CFG_GBL_DATA_SIZE	128		/* num bytes initial data*/
171 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
172 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
173 
174 #define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256kB for Mon */
175 #define CFG_MALLOC_LEN		(4 << 20)	/* Reserve 4 MB for malloc */
176 
177 /* FPGA and NAND */
178 #define CFG_FPGA_BASE		0xc0000000
179 #define CFG_FPGA_SIZE		0x00100000	/* 1 MB		*/
180 #define CFG_HMI_BASE		0xc0010000
181 #define CFG_BR3_PRELIM		0xc0001881	/* UPMA, 32-bit */
182 #define CFG_OR3_PRELIM		0xfff00000	/* 1 MB 	*/
183 
184 #define CFG_NAND_BASE		(CFG_FPGA_BASE + 0x70)
185 #define CFG_MAX_NAND_DEVICE	1
186 #define NAND_MAX_CHIPS		1
187 #define CONFIG_CMD_NAND
188 
189 /* LIME GDC */
190 #define CFG_LIME_BASE		0xc8000000
191 #define CFG_LIME_SIZE		0x04000000	/* 64 MB	*/
192 #define CFG_BR2_PRELIM		0xc80018a1	/* UPMB, 32-bit	*/
193 #define CFG_OR2_PRELIM		0xfc000000	/* 64 MB	*/
194 
195 #define CONFIG_VIDEO
196 #define CONFIG_VIDEO_MB862xx
197 #define CONFIG_CFB_CONSOLE
198 #define CONFIG_VIDEO_LOGO
199 #define CONFIG_VIDEO_BMP_LOGO
200 #define CONFIG_CONSOLE_EXTRA_INFO
201 #define VIDEO_FB_16BPP_PIXEL_SWAP
202 #define CONFIG_VGA_AS_SINGLE_DEVICE
203 #define CFG_CONSOLE_IS_IN_ENV
204 #define CONFIG_VIDEO_SW_CURSOR
205 #define CONFIG_SPLASH_SCREEN
206 #define CONFIG_VIDEO_BMP_GZIP
207 #define CFG_VIDEO_LOGO_MAX_SIZE	(2 << 20)	/* decompressed img */
208 
209 /* Serial Port */
210 
211 #define CONFIG_CONS_INDEX     1
212 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
213 #define CFG_NS16550
214 #define CFG_NS16550_SERIAL
215 #define CFG_NS16550_REG_SIZE	1
216 #define CFG_NS16550_CLK		get_bus_freq(0)
217 
218 #define CFG_NS16550_COM1	(CFG_CCSRBAR+0x4500)
219 #define CFG_NS16550_COM2	(CFG_CCSRBAR+0x4600)
220 
221 #define CONFIG_BAUDRATE         115200
222 
223 #define CFG_BAUDRATE_TABLE  \
224 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
225 
226 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
227 #define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
228 #ifdef	CFG_HUSH_PARSER
229 #define	CFG_PROMPT_HUSH_PS2	"> "
230 #endif
231 
232 
233 /*
234  * I2C
235  */
236 #define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
237 #define CONFIG_HARD_I2C			/* I2C with hardware support	*/
238 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
239 #define CFG_I2C_SPEED		102124	/* I2C speed and slave address	*/
240 #define CFG_I2C_SLAVE		0x7F
241 #define CFG_I2C_OFFSET		0x3000
242 
243 #define CONFIG_I2C_MULTI_BUS
244 #define CONFIG_I2C_CMD_TREE
245 #define CFG_I2C2_OFFSET		0x3100
246 
247 /* I2C RTC */
248 #define CONFIG_RTC_RX8025		/* Use Epson rx8025 rtc via i2c	*/
249 #define CFG_I2C_RTC_ADDR	0x32	/* at address 0x32		*/
250 
251 /* I2C W83782G HW-Monitoring IC */
252 #define CFG_I2C_W83782G_ADDR	0x28	/* W83782G address 		*/
253 
254 /* I2C temp sensor */
255 /* Socrates uses Maxim's	DS75, which is compatible with LM75 */
256 #define CONFIG_DTT_LM75		1
257 #define CONFIG_DTT_SENSORS	{4}		/* Sensor addresses	*/
258 #define CFG_DTT_MAX_TEMP	125
259 #define CFG_DTT_LOW_TEMP	-55
260 #define CFG_DTT_HYSTERESIS	3
261 #define CFG_EEPROM_PAGE_WRITE_ENABLE	/* necessary for the LM75 chip */
262 #define CFG_EEPROM_PAGE_WRITE_BITS	4
263 
264 /*
265  * General PCI
266  * Memory space is mapped 1-1.
267  */
268 #define CFG_PCI_PHYS		0x80000000	/* 1G PCI TLB */
269 
270 /* PCI is clocked by the external source at 33 MHz */
271 #define CONFIG_PCI_CLK_FREQ	33000000
272 #define CFG_PCI1_MEM_BASE	0x80000000
273 #define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
274 #define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M			*/
275 #define CFG_PCI1_IO_BASE	0xE2000000
276 #define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
277 #define CFG_PCI1_IO_SIZE	0x01000000	/* 16M			*/
278 
279 #if defined(CONFIG_PCI)
280 #define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
281 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
282 #endif	/* CONFIG_PCI */
283 
284 
285 #define CONFIG_NET_MULTI	1
286 #define CONFIG_MII		1	/* MII PHY management */
287 #define CONFIG_TSEC1	1
288 #define CONFIG_TSEC1_NAME	"TSEC0"
289 #define CONFIG_TSEC3	1
290 #define CONFIG_TSEC3_NAME	"TSEC1"
291 #undef CONFIG_MPC85XX_FEC
292 
293 #define TSEC1_PHY_ADDR		0
294 #define TSEC3_PHY_ADDR		1
295 
296 #define TSEC1_PHYIDX		0
297 #define TSEC3_PHYIDX		0
298 #define TSEC1_FLAGS		TSEC_GIGABIT
299 #define TSEC3_FLAGS		TSEC_GIGABIT
300 
301 /* Options are: TSEC[0,1] */
302 #define CONFIG_ETHPRIME		"TSEC0"
303 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
304 
305 #define CONFIG_HAS_ETH0
306 #define CONFIG_HAS_ETH1
307 
308 /*
309  * Environment
310  */
311 #define CFG_ENV_IS_IN_FLASH	1
312 #define CFG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env	*/
313 #define CFG_ENV_ADDR		(CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
314 #define CFG_ENV_SIZE		0x4000
315 #define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
316 #define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
317 
318 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
319 #define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
320 
321 #define	CONFIG_TIMESTAMP		/* Print image info with ts	*/
322 
323 
324 /*
325  * BOOTP options
326  */
327 #define CONFIG_BOOTP_BOOTFILESIZE
328 #define CONFIG_BOOTP_BOOTPATH
329 #define CONFIG_BOOTP_GATEWAY
330 #define CONFIG_BOOTP_HOSTNAME
331 
332 
333 /*
334  * Command line configuration.
335  */
336 #include <config_cmd_default.h>
337 
338 #define CONFIG_CMD_DATE
339 #define CONFIG_CMD_DHCP
340 #define CONFIG_CMD_DTT
341 #undef CONFIG_CMD_EEPROM
342 #define CONFIG_CMD_I2C
343 #define CONFIG_CMD_SDRAM
344 #define CONFIG_CMD_MII
345 #define CONFIG_CMD_NFS
346 #define CONFIG_CMD_PING
347 #define CONFIG_CMD_SNTP
348 #define CONFIG_CMD_USB
349 #define CONFIG_CMD_EXT2		/* EXT2 Support			*/
350 #define CONFIG_CMD_BMP
351 
352 #if defined(CONFIG_PCI)
353     #define CONFIG_CMD_PCI
354 #endif
355 
356 #undef CONFIG_WATCHDOG			/* watchdog disabled		*/
357 
358 /*
359  * Miscellaneous configurable options
360  */
361 #define CFG_LONGHELP			/* undef to save memory		*/
362 #define CFG_LOAD_ADDR	0x2000000	/* default load address		*/
363 #define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
364 
365 #if defined(CONFIG_CMD_KGDB)
366     #define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
367 #else
368     #define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
369 #endif
370 
371 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buf Size	*/
372 #define CFG_MAXARGS	16		/* max number of command args	*/
373 #define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
374 #define CFG_HZ		1000		/* decrementer freq: 1ms ticks	*/
375 
376 /*
377  * For booting Linux, the board info and command line data
378  * have to be in the first 8 MB of memory, since this is
379  * the maximum mapped by the Linux kernel during initialization.
380  */
381 #define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux	*/
382 
383 /*
384  * Internal Definitions
385  *
386  * Boot Flags
387  */
388 #define BOOTFLAG_COLD	0x01		/* Power-On: Boot from FLASH	*/
389 #define BOOTFLAG_WARM	0x02		/* Software reboot		*/
390 
391 #if defined(CONFIG_CMD_KGDB)
392 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port*/
393 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use	*/
394 #endif
395 
396 
397 #define CONFIG_LOADADDR	 200000		/* default addr for tftp & bootm*/
398 
399 #define CONFIG_BOOTDELAY 1		/* -1 disables auto-boot	*/
400 
401 #define CONFIG_PREBOOT	"echo;"	\
402 	"echo Welcome on the ABB Socrates Board;" \
403 	"echo"
404 
405 #undef	CONFIG_BOOTARGS		/* the boot command will set bootargs	*/
406 
407 #define	CONFIG_EXTRA_ENV_SETTINGS					\
408 	"netdev=eth0\0"							\
409 	"consdev=ttyS0\0"						\
410 	"uboot_file=/home/tftp/syscon3/u-boot.bin\0"			\
411 	"bootfile=/home/tftp/syscon3/uImage\0"				\
412 	"fdt_file=/home/tftp/syscon3/socrates.dtb\0"			\
413 	"initrd_file=/home/tftp/syscon3/uinitrd.gz\0"			\
414 	"uboot_addr=FFFA0000\0"						\
415 	"kernel_addr=FE000000\0"					\
416 	"fdt_addr=FE1E0000\0"						\
417 	"ramdisk_addr=FE200000\0"					\
418 	"fdt_addr_r=B00000\0"						\
419 	"kernel_addr_r=200000\0"					\
420 	"ramdisk_addr_r=400000\0"					\
421 	"rootpath=/opt/eldk/ppc_85xxDP\0"				\
422 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
423 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
424 		"nfsroot=$serverip:$rootpath\0"				\
425 	"addcons=setenv bootargs $bootargs "				\
426 		"console=$consdev,$baudrate\0"				\
427 	"addip=setenv bootargs $bootargs "				\
428 		"ip=$ipaddr:$serverip:$gatewayip:$netmask"		\
429 		":$hostname:$netdev:off panic=1\0"			\
430 	"boot_nor=run ramargs addcons;"					\
431 		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
432 	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
433 		"tftp ${fdt_addr_r} ${fdt_file}; "			\
434 		"run nfsargs addip addcons;"				\
435 		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
436 	"update_uboot=tftp 100000 ${uboot_file};"			\
437 		"protect off fffa0000 ffffffff;"			\
438 		"era fffa0000 ffffffff;"				\
439 		"cp.b 100000 fffa0000 ${filesize};"			\
440 		"setenv filesize;saveenv\0"				\
441 	"update_kernel=tftp 100000 ${bootfile};"			\
442 		"era fe000000 fe1dffff;"				\
443 		"cp.b 100000 fe000000 ${filesize};"			\
444 		"setenv filesize;saveenv\0"				\
445 	"update_fdt=tftp 100000 ${fdt_file};" 				\
446 		"era fe1e0000 fe1fffff;"				\
447 		"cp.b 100000 fe1e0000 ${filesize};"			\
448 		"setenv filesize;saveenv\0"				\
449 	"update_initrd=tftp 100000 ${initrd_file};" 			\
450 		"era fe200000 fe9fffff;"				\
451 		"cp.b 100000 fe200000 ${filesize};"			\
452 		"setenv filesize;saveenv\0"				\
453 	"clean_data=era fea00000 fff5ffff\0"				\
454 	"usbargs=setenv bootargs root=/dev/sda1 rw\0" 			\
455 	"load_usb=usb start;" 						\
456 		"ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0"	\
457 	"boot_usb=run load_usb usbargs addcons;"			\
458 		"bootm ${kernel_addr_r} - ${fdt_addr};"			\
459 		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
460 	""
461 #define CONFIG_BOOTCOMMAND	"run boot_nor"
462 
463 /* pass open firmware flat tree */
464 #define CONFIG_OF_LIBFDT	1
465 #define CONFIG_OF_BOARD_SETUP	1
466 
467 /* USB support */
468 #define CONFIG_USB_OHCI_NEW		1
469 #define CONFIG_PCI_OHCI			1
470 #define CONFIG_PCI_OHCI_DEVNO		3 /* Number in PCI list */
471 #define CONFIG_PCI_EHCI_DEVNO		(CONFIG_PCI_OHCI_DEVNO / 2)
472 #define CFG_USB_OHCI_MAX_ROOT_PORTS	15
473 #define CFG_USB_OHCI_SLOT_NAME		"ohci_pci"
474 #define CFG_OHCI_SWAP_REG_ACCESS	1
475 #define CONFIG_DOS_PARTITION		1
476 #define CONFIG_USB_STORAGE		1
477 
478 #endif	/* __CONFIG_H */
479