1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2008 4 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. 5 * 6 * Wolfgang Denk <wd@denx.de> 7 * Copyright 2004 Freescale Semiconductor. 8 * (C) Copyright 2002,2003 Motorola,Inc. 9 * Xianghua Xiao <X.Xiao@motorola.com> 10 */ 11 12 /* 13 * Socrates 14 */ 15 16 #ifndef __CONFIG_H 17 #define __CONFIG_H 18 19 /* High Level Configuration Options */ 20 #define CONFIG_SOCRATES 1 21 22 #define CONFIG_PCI_INDIRECT_BRIDGE 23 24 /* 25 * Only possible on E500 Version 2 or newer cores. 26 */ 27 #define CONFIG_ENABLE_36BIT_PHYS 1 28 29 /* 30 * sysclk for MPC85xx 31 * 32 * Two valid values are: 33 * 33000000 34 * 66000000 35 * 36 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 37 * is likely the desired value here, so that is now the default. 38 * The board, however, can run at 66MHz. In any event, this value 39 * must match the settings of some switches. Details can be found 40 * in the README.mpc85xxads. 41 */ 42 43 #ifndef CONFIG_SYS_CLK_FREQ 44 #define CONFIG_SYS_CLK_FREQ 66666666 45 #endif 46 47 /* 48 * These can be toggled for performance analysis, otherwise use default. 49 */ 50 #define CONFIG_L2_CACHE /* toggle L2 cache */ 51 #define CONFIG_BTB /* toggle branch predition */ 52 53 #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ 54 55 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 56 #define CONFIG_SYS_MEMTEST_START 0x00400000 57 #define CONFIG_SYS_MEMTEST_END 0x00C00000 58 59 #define CONFIG_SYS_CCSRBAR 0xE0000000 60 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 61 62 /* DDR Setup */ 63 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 64 #define CONFIG_DDR_SPD 65 66 #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 67 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 68 69 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 70 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 71 #define CONFIG_VERY_BIG_RAM 72 73 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 74 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 75 76 /* I2C addresses of SPD EEPROMs */ 77 #define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */ 78 79 #define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ 80 81 /* Hardcoded values, to use instead of SPD */ 82 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f 83 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 84 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 85 #define CONFIG_SYS_DDR_TIMING_1 0x3935D322 86 #define CONFIG_SYS_DDR_TIMING_2 0x14904CC8 87 #define CONFIG_SYS_DDR_MODE 0x00480432 88 #define CONFIG_SYS_DDR_INTERVAL 0x030C0100 89 #define CONFIG_SYS_DDR_CONFIG_2 0x04400000 90 #define CONFIG_SYS_DDR_CONFIG 0xC3008000 91 #define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000 92 #define CONFIG_SYS_SDRAM_SIZE 256 /* in Megs */ 93 94 /* 95 * Flash on the LocalBus 96 */ 97 #define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ 98 99 #define CONFIG_SYS_FLASH0 0xFE000000 100 #define CONFIG_SYS_FLASH1 0xFC000000 101 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 } 102 103 #define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */ 104 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */ 105 106 #define CONFIG_SYS_BR0_PRELIM 0xfe001001 /* port size 16bit */ 107 #define CONFIG_SYS_OR0_PRELIM 0xfe000030 /* 32MB Flash */ 108 #define CONFIG_SYS_BR1_PRELIM 0xfc001001 /* port size 16bit */ 109 #define CONFIG_SYS_OR1_PRELIM 0xfe000030 /* 32MB Flash */ 110 111 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 112 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ 113 #undef CONFIG_SYS_FLASH_CHECKSUM 114 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 115 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 116 117 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 118 119 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 120 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 121 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 122 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ 123 124 #define CONFIG_SYS_INIT_RAM_LOCK 1 125 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 126 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/ 127 128 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 129 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 130 131 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384KiB for Mon */ 132 #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */ 133 134 /* FPGA and NAND */ 135 #define CONFIG_SYS_FPGA_BASE 0xc0000000 136 #define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */ 137 #define CONFIG_SYS_HMI_BASE 0xc0010000 138 #define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */ 139 #define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */ 140 141 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70) 142 #define CONFIG_SYS_MAX_NAND_DEVICE 1 143 144 /* LIME GDC */ 145 #define CONFIG_SYS_LIME_BASE 0xc8000000 146 #define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */ 147 #define CONFIG_SYS_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */ 148 #define CONFIG_SYS_OR2_PRELIM 0xfc000000 /* 64 MB */ 149 150 #define CONFIG_VIDEO_MB862xx 151 #define CONFIG_VIDEO_MB862xx_ACCEL 152 #define CONFIG_VIDEO_LOGO 153 #define CONFIG_VIDEO_BMP_LOGO 154 #define VIDEO_FB_16BPP_PIXEL_SWAP 155 #define VIDEO_FB_16BPP_WORD_SWAP 156 #define CONFIG_SPLASH_SCREEN 157 #define CONFIG_VIDEO_BMP_GZIP 158 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */ 159 160 /* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */ 161 #define CONFIG_SYS_MB862xx_CCF 0x10000 162 /* SDRAM parameter */ 163 #define CONFIG_SYS_MB862xx_MMR 0x4157BA63 164 165 /* Serial Port */ 166 167 #define CONFIG_SYS_NS16550_SERIAL 168 #define CONFIG_SYS_NS16550_REG_SIZE 1 169 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 170 171 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 172 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 173 174 #define CONFIG_SYS_BAUDRATE_TABLE \ 175 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 176 177 /* 178 * I2C 179 */ 180 #define CONFIG_SYS_I2C 181 #define CONFIG_SYS_I2C_FSL 182 #define CONFIG_SYS_FSL_I2C_SPEED 102124 183 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 184 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 185 #define CONFIG_SYS_FSL_I2C2_SPEED 102124 186 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 187 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 188 189 /* I2C RTC */ 190 #define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */ 191 #define CONFIG_SYS_I2C_RTC_ADDR 0x32 /* at address 0x32 */ 192 193 /* I2C W83782G HW-Monitoring IC */ 194 #define CONFIG_SYS_I2C_W83782G_ADDR 0x28 /* W83782G address */ 195 196 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 197 198 /* 199 * General PCI 200 * Memory space is mapped 1-1. 201 */ 202 #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ 203 204 /* PCI is clocked by the external source at 33 MHz */ 205 #define CONFIG_PCI_CLK_FREQ 33000000 206 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 207 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 208 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 209 #define CONFIG_SYS_PCI1_IO_BASE 0xE2000000 210 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE 211 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ 212 213 #if defined(CONFIG_PCI) 214 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 215 #endif /* CONFIG_PCI */ 216 217 #define CONFIG_TSEC1 1 218 #define CONFIG_TSEC1_NAME "TSEC0" 219 #define CONFIG_TSEC3 1 220 #define CONFIG_TSEC3_NAME "TSEC1" 221 #undef CONFIG_MPC85XX_FEC 222 223 #define TSEC1_PHY_ADDR 0 224 #define TSEC3_PHY_ADDR 1 225 226 #define TSEC1_PHYIDX 0 227 #define TSEC3_PHYIDX 0 228 #define TSEC1_FLAGS TSEC_GIGABIT 229 #define TSEC3_FLAGS TSEC_GIGABIT 230 231 /* Options are: TSEC[0,1] */ 232 #define CONFIG_ETHPRIME "TSEC0" 233 234 #define CONFIG_HAS_ETH0 235 #define CONFIG_HAS_ETH1 236 237 /* 238 * Environment 239 */ 240 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 241 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 242 #define CONFIG_ENV_SIZE 0x4000 243 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) 244 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 245 246 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 247 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 248 249 #define CONFIG_TIMESTAMP /* Print image info with ts */ 250 251 /* 252 * BOOTP options 253 */ 254 #define CONFIG_BOOTP_BOOTFILESIZE 255 256 #undef CONFIG_WATCHDOG /* watchdog disabled */ 257 258 /* 259 * Miscellaneous configurable options 260 */ 261 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 262 263 /* 264 * For booting Linux, the board info and command line data 265 * have to be in the first 8 MB of memory, since this is 266 * the maximum mapped by the Linux kernel during initialization. 267 */ 268 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 269 270 #if defined(CONFIG_CMD_KGDB) 271 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/ 272 #endif 273 274 #define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/ 275 276 277 #define CONFIG_PREBOOT "echo;" \ 278 "echo Welcome on the ABB Socrates Board;" \ 279 "echo" 280 281 #define CONFIG_EXTRA_ENV_SETTINGS \ 282 "netdev=eth0\0" \ 283 "consdev=ttyS0\0" \ 284 "uboot_file=/home/tftp/syscon3/u-boot.bin\0" \ 285 "bootfile=/home/tftp/syscon3/uImage\0" \ 286 "fdt_file=/home/tftp/syscon3/socrates.dtb\0" \ 287 "initrd_file=/home/tftp/syscon3/uinitrd.gz\0" \ 288 "uboot_addr=FFFA0000\0" \ 289 "kernel_addr=FE000000\0" \ 290 "fdt_addr=FE1E0000\0" \ 291 "ramdisk_addr=FE200000\0" \ 292 "fdt_addr_r=B00000\0" \ 293 "kernel_addr_r=200000\0" \ 294 "ramdisk_addr_r=400000\0" \ 295 "rootpath=/opt/eldk/ppc_85xxDP\0" \ 296 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 297 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 298 "nfsroot=$serverip:$rootpath\0" \ 299 "addcons=setenv bootargs $bootargs " \ 300 "console=$consdev,$baudrate\0" \ 301 "addip=setenv bootargs $bootargs " \ 302 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ 303 ":$hostname:$netdev:off panic=1\0" \ 304 "boot_nor=run ramargs addcons;" \ 305 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 306 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 307 "tftp ${fdt_addr_r} ${fdt_file}; " \ 308 "run nfsargs addip addcons;" \ 309 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 310 "update_uboot=tftp 100000 ${uboot_file};" \ 311 "protect off fffa0000 ffffffff;" \ 312 "era fffa0000 ffffffff;" \ 313 "cp.b 100000 fffa0000 ${filesize};" \ 314 "setenv filesize;saveenv\0" \ 315 "update_kernel=tftp 100000 ${bootfile};" \ 316 "era fe000000 fe1dffff;" \ 317 "cp.b 100000 fe000000 ${filesize};" \ 318 "setenv filesize;saveenv\0" \ 319 "update_fdt=tftp 100000 ${fdt_file};" \ 320 "era fe1e0000 fe1fffff;" \ 321 "cp.b 100000 fe1e0000 ${filesize};" \ 322 "setenv filesize;saveenv\0" \ 323 "update_initrd=tftp 100000 ${initrd_file};" \ 324 "era fe200000 fe9fffff;" \ 325 "cp.b 100000 fe200000 ${filesize};" \ 326 "setenv filesize;saveenv\0" \ 327 "clean_data=era fea00000 fff5ffff\0" \ 328 "usbargs=setenv bootargs root=/dev/sda1 rw\0" \ 329 "load_usb=usb start;" \ 330 "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \ 331 "boot_usb=run load_usb usbargs addcons;" \ 332 "bootm ${kernel_addr_r} - ${fdt_addr};" \ 333 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 334 "" 335 #define CONFIG_BOOTCOMMAND "run boot_nor" 336 337 /* pass open firmware flat tree */ 338 339 /* USB support */ 340 #define CONFIG_USB_OHCI_NEW 1 341 #define CONFIG_PCI_OHCI 1 342 #define CONFIG_PCI_OHCI_DEVNO 3 /* Number in PCI list */ 343 #define CONFIG_PCI_EHCI_DEVNO (CONFIG_PCI_OHCI_DEVNO / 2) 344 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 345 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" 346 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 347 348 #endif /* __CONFIG_H */ 349