1 /* 2 * (C) Copyright 2008 3 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. 4 * 5 * Wolfgang Denk <wd@denx.de> 6 * Copyright 2004 Freescale Semiconductor. 7 * (C) Copyright 2002,2003 Motorola,Inc. 8 * Xianghua Xiao <X.Xiao@motorola.com> 9 * 10 * See file CREDITS for list of people who contributed to this 11 * project. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26 * MA 02111-1307 USA 27 */ 28 29 /* 30 * Socrates 31 */ 32 33 #ifndef __CONFIG_H 34 #define __CONFIG_H 35 36 /* new uImage format support */ 37 #define CONFIG_FIT 1 38 #define CONFIG_OF_LIBFDT 1 39 #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ 40 41 /* High Level Configuration Options */ 42 #define CONFIG_BOOKE 1 /* BOOKE */ 43 #define CONFIG_E500 1 /* BOOKE e500 family */ 44 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ 45 #define CONFIG_MPC8544 1 46 #define CONFIG_SOCRATES 1 47 48 #define CONFIG_SYS_TEXT_BASE 0xfff80000 49 50 #define CONFIG_PCI 51 #define CONFIG_PCI_INDIRECT_BRIDGE 52 53 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 54 55 #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ 56 #define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */ 57 58 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 59 60 /* 61 * Only possible on E500 Version 2 or newer cores. 62 */ 63 #define CONFIG_ENABLE_36BIT_PHYS 1 64 65 /* 66 * sysclk for MPC85xx 67 * 68 * Two valid values are: 69 * 33000000 70 * 66000000 71 * 72 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 73 * is likely the desired value here, so that is now the default. 74 * The board, however, can run at 66MHz. In any event, this value 75 * must match the settings of some switches. Details can be found 76 * in the README.mpc85xxads. 77 */ 78 79 #ifndef CONFIG_SYS_CLK_FREQ 80 #define CONFIG_SYS_CLK_FREQ 66666666 81 #endif 82 83 /* 84 * These can be toggled for performance analysis, otherwise use default. 85 */ 86 #define CONFIG_L2_CACHE /* toggle L2 cache */ 87 #define CONFIG_BTB /* toggle branch predition */ 88 89 #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ 90 91 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 92 #define CONFIG_SYS_MEMTEST_START 0x00400000 93 #define CONFIG_SYS_MEMTEST_END 0x00C00000 94 95 #define CONFIG_SYS_CCSRBAR 0xE0000000 96 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 97 98 /* DDR Setup */ 99 #define CONFIG_FSL_DDR2 100 #undef CONFIG_FSL_DDR_INTERACTIVE 101 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 102 #define CONFIG_DDR_SPD 103 104 #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 105 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 106 107 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 108 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 109 #define CONFIG_VERY_BIG_RAM 110 111 #define CONFIG_NUM_DDR_CONTROLLERS 1 112 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 113 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 114 115 /* I2C addresses of SPD EEPROMs */ 116 #define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */ 117 118 #define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ 119 120 /* Hardcoded values, to use instead of SPD */ 121 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f 122 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 123 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 124 #define CONFIG_SYS_DDR_TIMING_1 0x3935D322 125 #define CONFIG_SYS_DDR_TIMING_2 0x14904CC8 126 #define CONFIG_SYS_DDR_MODE 0x00480432 127 #define CONFIG_SYS_DDR_INTERVAL 0x030C0100 128 #define CONFIG_SYS_DDR_CONFIG_2 0x04400000 129 #define CONFIG_SYS_DDR_CONFIG 0xC3008000 130 #define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000 131 #define CONFIG_SYS_SDRAM_SIZE 256 /* in Megs */ 132 133 /* 134 * Flash on the LocalBus 135 */ 136 #define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ 137 138 #define CONFIG_SYS_FLASH0 0xFE000000 139 #define CONFIG_SYS_FLASH1 0xFC000000 140 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 } 141 142 #define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */ 143 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */ 144 145 #define CONFIG_SYS_BR0_PRELIM 0xfe001001 /* port size 16bit */ 146 #define CONFIG_SYS_OR0_PRELIM 0xfe000030 /* 32MB Flash */ 147 #define CONFIG_SYS_BR1_PRELIM 0xfc001001 /* port size 16bit */ 148 #define CONFIG_SYS_OR1_PRELIM 0xfe000030 /* 32MB Flash */ 149 150 #define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */ 151 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/ 152 153 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 154 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ 155 #undef CONFIG_SYS_FLASH_CHECKSUM 156 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 157 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 158 159 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 160 161 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 162 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 163 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 164 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ 165 166 #define CONFIG_SYS_INIT_RAM_LOCK 1 167 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 168 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/ 169 170 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 171 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 172 173 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384KiB for Mon */ 174 #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */ 175 176 /* FPGA and NAND */ 177 #define CONFIG_SYS_FPGA_BASE 0xc0000000 178 #define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */ 179 #define CONFIG_SYS_HMI_BASE 0xc0010000 180 #define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */ 181 #define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */ 182 183 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70) 184 #define CONFIG_SYS_MAX_NAND_DEVICE 1 185 #define CONFIG_CMD_NAND 186 187 /* LIME GDC */ 188 #define CONFIG_SYS_LIME_BASE 0xc8000000 189 #define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */ 190 #define CONFIG_SYS_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */ 191 #define CONFIG_SYS_OR2_PRELIM 0xfc000000 /* 64 MB */ 192 193 #define CONFIG_VIDEO 194 #define CONFIG_VIDEO_MB862xx 195 #define CONFIG_VIDEO_MB862xx_ACCEL 196 #define CONFIG_CFB_CONSOLE 197 #define CONFIG_VIDEO_LOGO 198 #define CONFIG_VIDEO_BMP_LOGO 199 #define CONFIG_CONSOLE_EXTRA_INFO 200 #define VIDEO_FB_16BPP_PIXEL_SWAP 201 #define VIDEO_FB_16BPP_WORD_SWAP 202 #define CONFIG_VGA_AS_SINGLE_DEVICE 203 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 204 #define CONFIG_VIDEO_SW_CURSOR 205 #define CONFIG_SPLASH_SCREEN 206 #define CONFIG_VIDEO_BMP_GZIP 207 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */ 208 209 /* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */ 210 #define CONFIG_SYS_MB862xx_CCF 0x10000 211 /* SDRAM parameter */ 212 #define CONFIG_SYS_MB862xx_MMR 0x4157BA63 213 214 /* Serial Port */ 215 216 #define CONFIG_CONS_INDEX 1 217 #define CONFIG_SYS_NS16550 218 #define CONFIG_SYS_NS16550_SERIAL 219 #define CONFIG_SYS_NS16550_REG_SIZE 1 220 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 221 222 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 223 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 224 225 #define CONFIG_BAUDRATE 115200 226 227 #define CONFIG_SYS_BAUDRATE_TABLE \ 228 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 229 230 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 231 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ 232 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ 233 234 235 /* 236 * I2C 237 */ 238 #define CONFIG_SYS_I2C 239 #define CONFIG_SYS_I2C_FSL 240 #define CONFIG_SYS_FSL_I2C_SPEED 102124 241 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 242 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 243 #define CONFIG_SYS_FSL_I2C2_SPEED 102124 244 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 245 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 246 247 /* I2C RTC */ 248 #define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */ 249 #define CONFIG_SYS_I2C_RTC_ADDR 0x32 /* at address 0x32 */ 250 251 /* I2C W83782G HW-Monitoring IC */ 252 #define CONFIG_SYS_I2C_W83782G_ADDR 0x28 /* W83782G address */ 253 254 /* I2C temp sensor */ 255 /* Socrates uses Maxim's DS75, which is compatible with LM75 */ 256 #define CONFIG_DTT_LM75 1 257 #define CONFIG_DTT_SENSORS {4} /* Sensor addresses */ 258 #define CONFIG_SYS_DTT_MAX_TEMP 125 259 #define CONFIG_SYS_DTT_LOW_TEMP -55 260 #define CONFIG_SYS_DTT_HYSTERESIS 3 261 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 262 263 /* 264 * General PCI 265 * Memory space is mapped 1-1. 266 */ 267 #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ 268 269 /* PCI is clocked by the external source at 33 MHz */ 270 #define CONFIG_PCI_CLK_FREQ 33000000 271 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 272 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 273 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 274 #define CONFIG_SYS_PCI1_IO_BASE 0xE2000000 275 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE 276 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ 277 278 #if defined(CONFIG_PCI) 279 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 280 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 281 #endif /* CONFIG_PCI */ 282 283 284 #define CONFIG_MII 1 /* MII PHY management */ 285 #define CONFIG_TSEC1 1 286 #define CONFIG_TSEC1_NAME "TSEC0" 287 #define CONFIG_TSEC3 1 288 #define CONFIG_TSEC3_NAME "TSEC1" 289 #undef CONFIG_MPC85XX_FEC 290 291 #define TSEC1_PHY_ADDR 0 292 #define TSEC3_PHY_ADDR 1 293 294 #define TSEC1_PHYIDX 0 295 #define TSEC3_PHYIDX 0 296 #define TSEC1_FLAGS TSEC_GIGABIT 297 #define TSEC3_FLAGS TSEC_GIGABIT 298 299 /* Options are: TSEC[0,1] */ 300 #define CONFIG_ETHPRIME "TSEC0" 301 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 302 303 #define CONFIG_HAS_ETH0 304 #define CONFIG_HAS_ETH1 305 306 /* 307 * Environment 308 */ 309 #define CONFIG_ENV_IS_IN_FLASH 1 310 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 311 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 312 #define CONFIG_ENV_SIZE 0x4000 313 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) 314 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 315 316 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 317 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 318 319 #define CONFIG_TIMESTAMP /* Print image info with ts */ 320 321 322 /* 323 * BOOTP options 324 */ 325 #define CONFIG_BOOTP_BOOTFILESIZE 326 #define CONFIG_BOOTP_BOOTPATH 327 #define CONFIG_BOOTP_GATEWAY 328 #define CONFIG_BOOTP_HOSTNAME 329 330 331 /* 332 * Command line configuration. 333 */ 334 #include <config_cmd_default.h> 335 336 #define CONFIG_CMD_BMP 337 #define CONFIG_CMD_DATE 338 #define CONFIG_CMD_DHCP 339 #define CONFIG_CMD_DTT 340 #undef CONFIG_CMD_EEPROM 341 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 342 #define CONFIG_CMD_I2C 343 #define CONFIG_CMD_SDRAM 344 #define CONFIG_CMD_MII 345 #undef CONFIG_CMD_NFS 346 #define CONFIG_CMD_PING 347 #define CONFIG_CMD_SNTP 348 #define CONFIG_CMD_USB 349 #define CONFIG_CMD_REGINFO 350 351 #if defined(CONFIG_PCI) 352 #define CONFIG_CMD_PCI 353 #endif 354 355 #undef CONFIG_WATCHDOG /* watchdog disabled */ 356 357 /* 358 * Miscellaneous configurable options 359 */ 360 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 361 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 362 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 363 364 #if defined(CONFIG_CMD_KGDB) 365 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 366 #else 367 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 368 #endif 369 370 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buf Size */ 371 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 372 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 373 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 374 375 /* 376 * For booting Linux, the board info and command line data 377 * have to be in the first 8 MB of memory, since this is 378 * the maximum mapped by the Linux kernel during initialization. 379 */ 380 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 381 382 #if defined(CONFIG_CMD_KGDB) 383 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/ 384 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 385 #endif 386 387 388 #define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/ 389 390 #define CONFIG_BOOTDELAY 1 /* -1 disables auto-boot */ 391 392 #define CONFIG_PREBOOT "echo;" \ 393 "echo Welcome on the ABB Socrates Board;" \ 394 "echo" 395 396 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 397 398 #define CONFIG_EXTRA_ENV_SETTINGS \ 399 "netdev=eth0\0" \ 400 "consdev=ttyS0\0" \ 401 "uboot_file=/home/tftp/syscon3/u-boot.bin\0" \ 402 "bootfile=/home/tftp/syscon3/uImage\0" \ 403 "fdt_file=/home/tftp/syscon3/socrates.dtb\0" \ 404 "initrd_file=/home/tftp/syscon3/uinitrd.gz\0" \ 405 "uboot_addr=FFFA0000\0" \ 406 "kernel_addr=FE000000\0" \ 407 "fdt_addr=FE1E0000\0" \ 408 "ramdisk_addr=FE200000\0" \ 409 "fdt_addr_r=B00000\0" \ 410 "kernel_addr_r=200000\0" \ 411 "ramdisk_addr_r=400000\0" \ 412 "rootpath=/opt/eldk/ppc_85xxDP\0" \ 413 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 414 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 415 "nfsroot=$serverip:$rootpath\0" \ 416 "addcons=setenv bootargs $bootargs " \ 417 "console=$consdev,$baudrate\0" \ 418 "addip=setenv bootargs $bootargs " \ 419 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ 420 ":$hostname:$netdev:off panic=1\0" \ 421 "boot_nor=run ramargs addcons;" \ 422 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 423 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 424 "tftp ${fdt_addr_r} ${fdt_file}; " \ 425 "run nfsargs addip addcons;" \ 426 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 427 "update_uboot=tftp 100000 ${uboot_file};" \ 428 "protect off fffa0000 ffffffff;" \ 429 "era fffa0000 ffffffff;" \ 430 "cp.b 100000 fffa0000 ${filesize};" \ 431 "setenv filesize;saveenv\0" \ 432 "update_kernel=tftp 100000 ${bootfile};" \ 433 "era fe000000 fe1dffff;" \ 434 "cp.b 100000 fe000000 ${filesize};" \ 435 "setenv filesize;saveenv\0" \ 436 "update_fdt=tftp 100000 ${fdt_file};" \ 437 "era fe1e0000 fe1fffff;" \ 438 "cp.b 100000 fe1e0000 ${filesize};" \ 439 "setenv filesize;saveenv\0" \ 440 "update_initrd=tftp 100000 ${initrd_file};" \ 441 "era fe200000 fe9fffff;" \ 442 "cp.b 100000 fe200000 ${filesize};" \ 443 "setenv filesize;saveenv\0" \ 444 "clean_data=era fea00000 fff5ffff\0" \ 445 "usbargs=setenv bootargs root=/dev/sda1 rw\0" \ 446 "load_usb=usb start;" \ 447 "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \ 448 "boot_usb=run load_usb usbargs addcons;" \ 449 "bootm ${kernel_addr_r} - ${fdt_addr};" \ 450 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 451 "" 452 #define CONFIG_BOOTCOMMAND "run boot_nor" 453 454 /* pass open firmware flat tree */ 455 #define CONFIG_OF_LIBFDT 1 456 #define CONFIG_OF_BOARD_SETUP 1 457 458 /* USB support */ 459 #define CONFIG_USB_OHCI_NEW 1 460 #define CONFIG_PCI_OHCI 1 461 #define CONFIG_PCI_OHCI_DEVNO 3 /* Number in PCI list */ 462 #define CONFIG_PCI_EHCI_DEVNO (CONFIG_PCI_OHCI_DEVNO / 2) 463 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 464 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" 465 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 466 #define CONFIG_DOS_PARTITION 1 467 #define CONFIG_USB_STORAGE 1 468 469 #endif /* __CONFIG_H */ 470