1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright (C) 2017-2018 Intel Corporation <www.intel.com> 4 * 5 */ 6 7 #ifndef __CONFIG_SOCFGPA_STRATIX10_H__ 8 #define __CONFIG_SOCFGPA_STRATIX10_H__ 9 10 #include <asm/arch/base_addr_s10.h> 11 #include <asm/arch/handoff_s10.h> 12 13 /* 14 * U-Boot general configurations 15 */ 16 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 17 #define CONFIG_LOADADDR 0x2000000 18 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 19 #define CONFIG_REMAKE_ELF 20 /* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */ 21 #define CPU_RELEASE_ADDR 0xFFD12210 22 #define CONFIG_SYS_CACHELINE_SIZE 64 23 #define CONFIG_SYS_MEM_RESERVE_SECURE 0 /* using OCRAM, not DDR */ 24 25 /* 26 * U-Boot console configurations 27 */ 28 #define CONFIG_SYS_MAXARGS 64 29 #define CONFIG_SYS_CBSIZE 2048 30 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 31 sizeof(CONFIG_SYS_PROMPT) + 16) 32 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 33 34 /* Extend size of kernel image for uncompression */ 35 #define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024) 36 37 /* 38 * U-Boot run time memory configurations 39 */ 40 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 41 #define CONFIG_SYS_INIT_RAM_SIZE 0x40000 42 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR \ 43 + CONFIG_SYS_INIT_RAM_SIZE \ 44 - S10_HANDOFF_SIZE) 45 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_SP_ADDR) 46 #define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) 47 48 /* 49 * U-Boot environment configurations 50 */ 51 #define CONFIG_ENV_SIZE 0x1000 52 #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ 53 #define CONFIG_ENV_OFFSET 512 /* just after the MBR */ 54 55 /* 56 * QSPI support 57 */ 58 #ifdef CONFIG_CADENCE_QSPI 59 /* Enable it if you want to use dual-stacked mode */ 60 /*#define CONFIG_QSPI_RBF_ADDR 0x720000*/ 61 62 /* Flash device info */ 63 #define CONFIG_SF_DEFAULT_SPEED (50000000) 64 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_3 | SPI_RX_QUAD) 65 #define CONFIG_SF_DEFAULT_BUS 0 66 #define CONFIG_SF_DEFAULT_CS 0 67 68 /*#define CONFIG_ENV_IS_IN_SPI_FLASH*/ 69 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH 70 #undef CONFIG_ENV_OFFSET 71 #undef CONFIG_ENV_SIZE 72 #define CONFIG_ENV_OFFSET 0x710000 73 #define CONFIG_ENV_SIZE (4 * 1024) 74 #define CONFIG_ENV_SECT_SIZE (4 * 1024) 75 #endif /* CONFIG_ENV_IS_IN_SPI_FLASH */ 76 77 #ifndef CONFIG_SPL_BUILD 78 #define CONFIG_MTD_DEVICE 79 #define CONFIG_MTD_PARTITIONS 80 #define MTDIDS_DEFAULT "nor0=ff705000.spi.0" 81 #endif /* CONFIG_SPL_BUILD */ 82 83 #ifndef __ASSEMBLY__ 84 unsigned int cm_get_qspi_controller_clk_hz(void); 85 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() 86 #endif 87 88 #endif /* CONFIG_CADENCE_QSPI */ 89 90 /* 91 * Boot arguments passed to the boot command. The value of 92 * CONFIG_BOOTARGS goes into the environment value "bootargs". 93 * Do note the value will override also the chosen node in FDT blob. 94 */ 95 #define CONFIG_BOOTARGS "earlycon" 96 #define CONFIG_BOOTCOMMAND "run fatscript; run mmcload;run linux_qspi_enable;" \ 97 "run mmcboot" 98 99 #define CONFIG_EXTRA_ENV_SETTINGS \ 100 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ 101 "bootfile=Image\0" \ 102 "fdt_addr=8000000\0" \ 103 "fdtimage=socfpga_stratix10_socdk.dtb\0" \ 104 "mmcroot=/dev/mmcblk0p2\0" \ 105 "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ 106 " root=${mmcroot} rw rootwait;" \ 107 "booti ${loadaddr} - ${fdt_addr}\0" \ 108 "mmcload=mmc rescan;" \ 109 "load mmc 0:1 ${loadaddr} ${bootfile};" \ 110 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ 111 "linux_qspi_enable=if sf probe; then " \ 112 "echo Enabling QSPI at Linux DTB...;" \ 113 "fdt addr ${fdt_addr}; fdt resize;" \ 114 "fdt set /soc/spi@ff8d2000 status okay;" \ 115 "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \ 116 " ${qspi_clock}; fi; \0" \ 117 "scriptaddr=0x02100000\0" \ 118 "scriptfile=u-boot.scr\0" \ 119 "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \ 120 "then source ${scriptaddr}; fi\0" 121 122 /* 123 * Generic Interrupt Controller Definitions 124 */ 125 #define CONFIG_GICV2 126 127 /* 128 * External memory configurations 129 */ 130 #define PHYS_SDRAM_1 0x0 131 #define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024) 132 #define CONFIG_SYS_SDRAM_BASE 0 133 #define CONFIG_SYS_MEMTEST_START 0 134 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE - 0x200000 135 136 /* 137 * SDRAM controller 138 */ 139 #define CONFIG_ALTERA_SDRAM 140 141 /* 142 * Serial / UART configurations 143 */ 144 #define CONFIG_SYS_NS16550_CLK 100000000 145 #define CONFIG_SYS_NS16550_MEM32 146 147 /* 148 * Timer & watchdog configurations 149 */ 150 #define COUNTER_FREQUENCY 400000000 151 152 /* 153 * SDMMC configurations 154 */ 155 #ifdef CONFIG_CMD_MMC 156 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 157 #endif 158 /* 159 * Flash configurations 160 */ 161 #define CONFIG_SYS_MAX_FLASH_BANKS 1 162 163 /* Ethernet on SoC (EMAC) */ 164 #if defined(CONFIG_CMD_NET) 165 #define CONFIG_DW_ALTDESCRIPTOR 166 #endif /* CONFIG_CMD_NET */ 167 168 /* 169 * L4 Watchdog 170 */ 171 #ifdef CONFIG_SPL_BUILD 172 #define CONFIG_HW_WATCHDOG 173 #define CONFIG_DESIGNWARE_WATCHDOG 174 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS 175 #ifndef __ASSEMBLY__ 176 unsigned int cm_get_l4_sys_free_clk_hz(void); 177 #define CONFIG_DW_WDT_CLOCK_KHZ (cm_get_l4_sys_free_clk_hz() / 1000) 178 #endif 179 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 3000 180 #endif 181 182 /* 183 * SPL memory layout 184 * 185 * On chip RAM 186 * 0xFFE0_0000 ...... Start of OCRAM 187 * SPL code, rwdata 188 * empty space 189 * 0xFFEx_xxxx ...... Top of stack (grows down) 190 * 0xFFEy_yyyy ...... Global Data 191 * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN) 192 * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB) 193 * 0xFFE3_FFFF ...... End of OCRAM 194 * 195 * SDRAM 196 * 0x0000_0000 ...... Start of SDRAM_1 197 * unused / empty space for image loading 198 * Size 64MB ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE) 199 * Size 1MB ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE) 200 * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB) 201 * 202 */ 203 #define CONFIG_SPL_TARGET "spl/u-boot-spl.hex" 204 #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR 205 #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE 206 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR 207 #define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ 208 #define CONFIG_SPL_BSS_START_ADDR (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \ 209 - CONFIG_SPL_BSS_MAX_SIZE) 210 #define CONFIG_SYS_SPL_MALLOC_SIZE (CONFIG_SYS_MALLOC_LEN) 211 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR \ 212 - CONFIG_SYS_SPL_MALLOC_SIZE) 213 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x3C00000 214 215 /* SPL SDMMC boot support */ 216 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 217 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 218 219 #endif /* __CONFIG_H */ 220