1 /* 2 * Copyright (C) 2015 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef __CONFIG_SOCFPGA_SR1500_H__ 7 #define __CONFIG_SOCFPGA_SR1500_H__ 8 9 #include <asm/arch/base_addr_ac5.h> 10 11 #define CONFIG_BOARD_EARLY_INIT_F 12 13 #define CONFIG_SYS_NO_FLASH 14 #define CONFIG_DOS_PARTITION 15 #define CONFIG_FAT_WRITE 16 17 #define CONFIG_HW_WATCHDOG 18 19 /* U-Boot Commands */ 20 #define CONFIG_CMD_ASKENV 21 #define CONFIG_CMD_BOOTZ 22 #define CONFIG_CMD_CACHE 23 #define CONFIG_CMD_DHCP 24 #define CONFIG_CMD_EXT4 25 #define CONFIG_CMD_EXT4_WRITE 26 #define CONFIG_CMD_FAT 27 #define CONFIG_CMD_FS_GENERIC 28 #define CONFIG_CMD_GPIO 29 #define CONFIG_CMD_GREPENV 30 #define CONFIG_CMD_MEMTEST 31 #define CONFIG_CMD_MII 32 #define CONFIG_CMD_MMC 33 #define CONFIG_CMD_PING 34 #define CONFIG_CMD_SF 35 #define CONFIG_CMD_SPI 36 #define CONFIG_CMD_TIME 37 38 /* Memory configurations */ 39 #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */ 40 41 /* Booting Linux */ 42 #define CONFIG_BOOTDELAY 3 43 #define CONFIG_BOOTFILE "uImage" 44 #define CONFIG_BOOTARGS "console=ttyS0" __stringify(CONFIG_BAUDRATE) 45 #define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" 46 #define CONFIG_LOADADDR 0x01000000 47 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 48 #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ 49 50 /* Ethernet on SoC (EMAC) */ 51 #define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII 52 /* The PHY is autodetected, so no MII PHY address is needed here */ 53 #define CONFIG_PHY_MARVELL 54 #define PHY_ANEG_TIMEOUT 8000 55 56 #define CONFIG_EXTRA_ENV_SETTINGS \ 57 "verify=n\0" \ 58 "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ 59 "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ 60 "bootm ${loadaddr} - ${fdt_addr}\0" \ 61 "bootimage=zImage\0" \ 62 "fdt_addr=100\0" \ 63 "fdtimage=socfpga.dtb\0" \ 64 "fsloadcmd=ext2load\0" \ 65 "bootm ${loadaddr} - ${fdt_addr}\0" \ 66 "mmcroot=/dev/mmcblk0p2\0" \ 67 "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ 68 " root=${mmcroot} rw rootwait;" \ 69 "bootz ${loadaddr} - ${fdt_addr}\0" \ 70 "mmcload=mmc rescan;" \ 71 "load mmc 0:1 ${loadaddr} ${bootimage};" \ 72 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ 73 "qspiroot=/dev/mtdblock0\0" \ 74 "qspirootfstype=jffs2\0" \ 75 "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ 76 " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ 77 "bootm ${loadaddr} - ${fdt_addr}\0" 78 79 /* Environment */ 80 #define CONFIG_ENV_IS_IN_SPI_FLASH 81 82 /* Enable SPI NOR flash reset, needed for SPI booting */ 83 #define CONFIG_SPI_N25Q256A_RESET 84 85 /* 86 * Bootcounter 87 */ 88 #define CONFIG_BOOTCOUNT_LIMIT 89 /* last 2 lwords in OCRAM */ 90 #define CONFIG_SYS_BOOTCOUNT_ADDR 0xfffffff8 91 #define CONFIG_SYS_BOOTCOUNT_BE 92 93 /* The rest of the configuration is shared */ 94 #include <configs/socfpga_common.h> 95 96 /* U-Boot payload is stored at offset 0x60000 */ 97 #undef CONFIG_SYS_SPI_U_BOOT_OFFS 98 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x60000 99 100 /* Environment setting for SPI flash */ 101 #undef CONFIG_ENV_SIZE 102 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 103 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 104 #define CONFIG_ENV_SIZE (16 * 1024) 105 #define CONFIG_ENV_OFFSET 0x00040000 106 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) 107 #define CONFIG_ENV_SPI_BUS 0 108 #define CONFIG_ENV_SPI_CS 0 109 #define CONFIG_ENV_SPI_MODE SPI_MODE_3 110 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 111 112 #endif /* __CONFIG_SOCFPGA_SR1500_H__ */ 113