1 /* 2 * Copyright (C) 2015 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef __CONFIG_SOCFPGA_SR1500_H__ 7 #define __CONFIG_SOCFPGA_SR1500_H__ 8 9 #include <asm/arch/base_addr_ac5.h> 10 11 #define CONFIG_SYS_NO_FLASH 12 #define CONFIG_FAT_WRITE 13 14 #define CONFIG_HW_WATCHDOG 15 16 /* Memory configurations */ 17 #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */ 18 19 /* Booting Linux */ 20 #define CONFIG_BOOTFILE "uImage" 21 #define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) 22 #define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" 23 #define CONFIG_LOADADDR 0x01000000 24 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 25 26 /* Ethernet on SoC (EMAC) */ 27 #define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII 28 /* The PHY is autodetected, so no MII PHY address is needed here */ 29 #define CONFIG_PHY_MARVELL 30 #define PHY_ANEG_TIMEOUT 8000 31 32 #define CONFIG_EXTRA_ENV_SETTINGS \ 33 "verify=n\0" \ 34 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ 35 "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ 36 "bootm ${loadaddr} - ${fdt_addr}\0" \ 37 "bootimage=zImage\0" \ 38 "fdt_addr=100\0" \ 39 "fdtimage=socfpga.dtb\0" \ 40 "fsloadcmd=ext2load\0" \ 41 "bootm ${loadaddr} - ${fdt_addr}\0" \ 42 "mmcroot=/dev/mmcblk0p2\0" \ 43 "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ 44 " root=${mmcroot} rw rootwait;" \ 45 "bootz ${loadaddr} - ${fdt_addr}\0" \ 46 "mmcload=mmc rescan;" \ 47 "load mmc 0:1 ${loadaddr} ${bootimage};" \ 48 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ 49 "qspiload=sf probe && mtdparts default && run ubiload\0" \ 50 "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ 51 " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\ 52 "bootz ${loadaddr} - ${fdt_addr}\0" \ 53 "ubiload=ubi part UBI && ubifsmount ubi0 && " \ 54 "ubifsload ${loadaddr} /boot/${bootimage} && " \ 55 "ubifsload ${fdt_addr} /boot/${fdtimage}\0" 56 57 /* Environment */ 58 #define CONFIG_ENV_IS_IN_SPI_FLASH 59 60 /* Enable SPI NOR flash reset, needed for SPI booting */ 61 #define CONFIG_SPI_N25Q256A_RESET 62 63 /* 64 * Bootcounter 65 */ 66 #define CONFIG_BOOTCOUNT_LIMIT 67 /* last 2 lwords in OCRAM */ 68 #define CONFIG_SYS_BOOTCOUNT_ADDR 0xfffffff8 69 #define CONFIG_SYS_BOOTCOUNT_BE 70 71 /* Environment setting for SPI flash */ 72 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 73 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 74 #define CONFIG_ENV_SIZE (16 * 1024) 75 #define CONFIG_ENV_OFFSET 0x000e0000 76 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) 77 #define CONFIG_ENV_SPI_BUS 0 78 #define CONFIG_ENV_SPI_CS 0 79 #define CONFIG_ENV_SPI_MODE SPI_MODE_3 80 #define CONFIG_ENV_SPI_MAX_HZ 100000000 /* Use max of 100MHz */ 81 #define CONFIG_SF_DEFAULT_SPEED 100000000 82 83 /* 84 * The QSPI NOR flash layout on SR1500: 85 * 86 * 0000.0000 - 0003.ffff: SPL (4 times) 87 * 0004.0000 - 000d.ffff: U-Boot 88 * 000e.0000 - 000e.ffff: env1 89 * 000f.0000 - 000f.ffff: env2 90 */ 91 92 /* The rest of the configuration is shared */ 93 #include <configs/socfpga_common.h> 94 95 #endif /* __CONFIG_SOCFPGA_SR1500_H__ */ 96