1 /* 2 * Copyright (C) 2015 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef __CONFIG_SOCFPGA_SR1500_H__ 7 #define __CONFIG_SOCFPGA_SR1500_H__ 8 9 #include <asm/arch/base_addr_ac5.h> 10 11 /* Memory configurations */ 12 #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */ 13 14 /* Booting Linux */ 15 #define CONFIG_LOADADDR 0x01000000 16 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 17 18 /* Ethernet on SoC (EMAC) */ 19 #define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII 20 /* The PHY is autodetected, so no MII PHY address is needed here */ 21 #define CONFIG_PHY_MARVELL 22 #define PHY_ANEG_TIMEOUT 8000 23 24 /* Environment */ 25 26 /* Enable SPI NOR flash reset, needed for SPI booting */ 27 #define CONFIG_SPI_N25Q256A_RESET 28 29 /* 30 * Bootcounter 31 */ 32 #define CONFIG_SYS_BOOTCOUNT_BE 33 34 /* Environment setting for SPI flash */ 35 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 36 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 37 #define CONFIG_ENV_SIZE (16 * 1024) 38 #define CONFIG_ENV_OFFSET 0x000e0000 39 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) 40 #define CONFIG_ENV_SPI_BUS 0 41 #define CONFIG_ENV_SPI_CS 0 42 #define CONFIG_ENV_SPI_MODE SPI_MODE_3 43 #define CONFIG_ENV_SPI_MAX_HZ 100000000 /* Use max of 100MHz */ 44 #define CONFIG_SF_DEFAULT_SPEED 100000000 45 46 /* 47 * The QSPI NOR flash layout on SR1500: 48 * 49 * 0000.0000 - 0003.ffff: SPL (4 times) 50 * 0004.0000 - 000d.ffff: U-Boot 51 * 000e.0000 - 000e.ffff: env1 52 * 000f.0000 - 000f.ffff: env2 53 */ 54 55 /* The rest of the configuration is shared */ 56 #include <configs/socfpga_common.h> 57 58 #endif /* __CONFIG_SOCFPGA_SR1500_H__ */ 59