1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2015 Stefan Roese <sr@denx.de>
4  */
5 #ifndef __CONFIG_SOCFPGA_SR1500_H__
6 #define __CONFIG_SOCFPGA_SR1500_H__
7 
8 #include <asm/arch/base_addr_ac5.h>
9 
10 /* Memory configurations */
11 #define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SR1500 */
12 
13 /* Booting Linux */
14 #define CONFIG_LOADADDR		0x01000000
15 #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
16 
17 /* Ethernet on SoC (EMAC) */
18 #define CONFIG_PHY_INTERFACE_MODE	PHY_INTERFACE_MODE_RGMII
19 /* The PHY is autodetected, so no MII PHY address is needed here */
20 #define PHY_ANEG_TIMEOUT	8000
21 
22 /* Environment */
23 
24 /* Enable SPI NOR flash reset, needed for SPI booting */
25 #define CONFIG_SPI_N25Q256A_RESET
26 
27 /*
28  * Bootcounter
29  */
30 #define CONFIG_SYS_BOOTCOUNT_BE
31 
32 /* Environment setting for SPI flash */
33 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
34 #define CONFIG_ENV_SECT_SIZE	(64 * 1024)
35 #define CONFIG_ENV_SIZE		(16 * 1024)
36 #define CONFIG_ENV_OFFSET	0x000e0000
37 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
38 #define CONFIG_ENV_SPI_BUS	0
39 #define CONFIG_ENV_SPI_CS	0
40 #define CONFIG_ENV_SPI_MODE	SPI_MODE_3
41 #define CONFIG_ENV_SPI_MAX_HZ	100000000	/* Use max of 100MHz */
42 #define CONFIG_SF_DEFAULT_SPEED	100000000
43 
44 /*
45  * The QSPI NOR flash layout on SR1500:
46  *
47  * 0000.0000 - 0003.ffff: SPL (4 times)
48  * 0004.0000 - 000d.ffff: U-Boot
49  * 000e.0000 - 000e.ffff: env1
50  * 000f.0000 - 000f.ffff: env2
51  */
52 
53 /* The rest of the configuration is shared */
54 #include <configs/socfpga_common.h>
55 
56 #endif	/* __CONFIG_SOCFPGA_SR1500_H__ */
57