1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2015 Stefan Roese <sr@denx.de> 4 */ 5 #ifndef __CONFIG_SOCFPGA_SR1500_H__ 6 #define __CONFIG_SOCFPGA_SR1500_H__ 7 8 #include <asm/arch/base_addr_ac5.h> 9 10 /* Memory configurations */ 11 #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */ 12 13 /* Booting Linux */ 14 #define CONFIG_LOADADDR 0x01000000 15 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 16 17 /* Ethernet on SoC (EMAC) */ 18 #define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII 19 /* The PHY is autodetected, so no MII PHY address is needed here */ 20 #define CONFIG_PHY_MARVELL 21 #define PHY_ANEG_TIMEOUT 8000 22 23 /* Environment */ 24 25 /* Enable SPI NOR flash reset, needed for SPI booting */ 26 #define CONFIG_SPI_N25Q256A_RESET 27 28 /* 29 * Bootcounter 30 */ 31 #define CONFIG_SYS_BOOTCOUNT_BE 32 33 /* Environment setting for SPI flash */ 34 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 35 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 36 #define CONFIG_ENV_SIZE (16 * 1024) 37 #define CONFIG_ENV_OFFSET 0x000e0000 38 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) 39 #define CONFIG_ENV_SPI_BUS 0 40 #define CONFIG_ENV_SPI_CS 0 41 #define CONFIG_ENV_SPI_MODE SPI_MODE_3 42 #define CONFIG_ENV_SPI_MAX_HZ 100000000 /* Use max of 100MHz */ 43 #define CONFIG_SF_DEFAULT_SPEED 100000000 44 45 /* 46 * The QSPI NOR flash layout on SR1500: 47 * 48 * 0000.0000 - 0003.ffff: SPL (4 times) 49 * 0004.0000 - 000d.ffff: U-Boot 50 * 000e.0000 - 000e.ffff: env1 51 * 000f.0000 - 000f.ffff: env2 52 */ 53 54 /* The rest of the configuration is shared */ 55 #include <configs/socfpga_common.h> 56 57 #endif /* __CONFIG_SOCFPGA_SR1500_H__ */ 58