1*ae9996c8SStefan Roese /* 2*ae9996c8SStefan Roese * Copyright (C) 2015 Stefan Roese <sr@denx.de> 3*ae9996c8SStefan Roese * 4*ae9996c8SStefan Roese * SPDX-License-Identifier: GPL-2.0+ 5*ae9996c8SStefan Roese */ 6*ae9996c8SStefan Roese #ifndef __CONFIG_SOCFPGA_SR1500_H__ 7*ae9996c8SStefan Roese #define __CONFIG_SOCFPGA_SR1500_H__ 8*ae9996c8SStefan Roese 9*ae9996c8SStefan Roese #include <asm/arch/base_addr_ac5.h> 10*ae9996c8SStefan Roese 11*ae9996c8SStefan Roese #define CONFIG_BOARD_EARLY_INIT_F 12*ae9996c8SStefan Roese 13*ae9996c8SStefan Roese #define CONFIG_SYS_NO_FLASH 14*ae9996c8SStefan Roese #define CONFIG_DOS_PARTITION 15*ae9996c8SStefan Roese #define CONFIG_FAT_WRITE 16*ae9996c8SStefan Roese 17*ae9996c8SStefan Roese #define CONFIG_HW_WATCHDOG 18*ae9996c8SStefan Roese 19*ae9996c8SStefan Roese /* U-Boot Commands */ 20*ae9996c8SStefan Roese #define CONFIG_CMD_ASKENV 21*ae9996c8SStefan Roese #define CONFIG_CMD_BOOTZ 22*ae9996c8SStefan Roese #define CONFIG_CMD_CACHE 23*ae9996c8SStefan Roese #define CONFIG_CMD_DHCP 24*ae9996c8SStefan Roese #define CONFIG_CMD_EXT4 25*ae9996c8SStefan Roese #define CONFIG_CMD_EXT4_WRITE 26*ae9996c8SStefan Roese #define CONFIG_CMD_FAT 27*ae9996c8SStefan Roese #define CONFIG_CMD_FS_GENERIC 28*ae9996c8SStefan Roese #define CONFIG_CMD_GPIO 29*ae9996c8SStefan Roese #define CONFIG_CMD_GREPENV 30*ae9996c8SStefan Roese #define CONFIG_CMD_MEMTEST 31*ae9996c8SStefan Roese #define CONFIG_CMD_MII 32*ae9996c8SStefan Roese #define CONFIG_CMD_MMC 33*ae9996c8SStefan Roese #define CONFIG_CMD_PING 34*ae9996c8SStefan Roese #define CONFIG_CMD_SF 35*ae9996c8SStefan Roese #define CONFIG_CMD_SPI 36*ae9996c8SStefan Roese #define CONFIG_CMD_TIME 37*ae9996c8SStefan Roese 38*ae9996c8SStefan Roese /* Memory configurations */ 39*ae9996c8SStefan Roese #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */ 40*ae9996c8SStefan Roese 41*ae9996c8SStefan Roese /* Booting Linux */ 42*ae9996c8SStefan Roese #define CONFIG_BOOTDELAY 3 43*ae9996c8SStefan Roese #define CONFIG_BOOTFILE "uImage" 44*ae9996c8SStefan Roese #define CONFIG_BOOTARGS "console=ttyS0" __stringify(CONFIG_BAUDRATE) 45*ae9996c8SStefan Roese #define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" 46*ae9996c8SStefan Roese #define CONFIG_LOADADDR 0x01000000 47*ae9996c8SStefan Roese #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 48*ae9996c8SStefan Roese #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ 49*ae9996c8SStefan Roese 50*ae9996c8SStefan Roese /* Ethernet on SoC (EMAC) */ 51*ae9996c8SStefan Roese #define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII 52*ae9996c8SStefan Roese /* The PHY is autodetected, so no MII PHY address is needed here */ 53*ae9996c8SStefan Roese #define CONFIG_PHY_MARVELL 54*ae9996c8SStefan Roese #define PHY_ANEG_TIMEOUT 8000 55*ae9996c8SStefan Roese 56*ae9996c8SStefan Roese /* Extra Environment */ 57*ae9996c8SStefan Roese #define CONFIG_HOSTNAME sr1500 58*ae9996c8SStefan Roese 59*ae9996c8SStefan Roese #define CONFIG_EXTRA_ENV_SETTINGS \ 60*ae9996c8SStefan Roese "verify=n\0" \ 61*ae9996c8SStefan Roese "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ 62*ae9996c8SStefan Roese "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ 63*ae9996c8SStefan Roese "bootm ${loadaddr} - ${fdt_addr}\0" \ 64*ae9996c8SStefan Roese "bootimage=zImage\0" \ 65*ae9996c8SStefan Roese "fdt_addr=100\0" \ 66*ae9996c8SStefan Roese "fdtimage=socfpga.dtb\0" \ 67*ae9996c8SStefan Roese "fsloadcmd=ext2load\0" \ 68*ae9996c8SStefan Roese "bootm ${loadaddr} - ${fdt_addr}\0" \ 69*ae9996c8SStefan Roese "mmcroot=/dev/mmcblk0p2\0" \ 70*ae9996c8SStefan Roese "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ 71*ae9996c8SStefan Roese " root=${mmcroot} rw rootwait;" \ 72*ae9996c8SStefan Roese "bootz ${loadaddr} - ${fdt_addr}\0" \ 73*ae9996c8SStefan Roese "mmcload=mmc rescan;" \ 74*ae9996c8SStefan Roese "load mmc 0:1 ${loadaddr} ${bootimage};" \ 75*ae9996c8SStefan Roese "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ 76*ae9996c8SStefan Roese "qspiroot=/dev/mtdblock0\0" \ 77*ae9996c8SStefan Roese "qspirootfstype=jffs2\0" \ 78*ae9996c8SStefan Roese "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ 79*ae9996c8SStefan Roese " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ 80*ae9996c8SStefan Roese "bootm ${loadaddr} - ${fdt_addr}\0" 81*ae9996c8SStefan Roese 82*ae9996c8SStefan Roese /* Environment */ 83*ae9996c8SStefan Roese #define CONFIG_ENV_IS_IN_SPI_FLASH 84*ae9996c8SStefan Roese 85*ae9996c8SStefan Roese /* Enable SPI NOR flash reset, needed for SPI booting */ 86*ae9996c8SStefan Roese #define CONFIG_SPI_N25Q256A_RESET 87*ae9996c8SStefan Roese 88*ae9996c8SStefan Roese /* 89*ae9996c8SStefan Roese * Bootcounter 90*ae9996c8SStefan Roese */ 91*ae9996c8SStefan Roese #define CONFIG_BOOTCOUNT_LIMIT 92*ae9996c8SStefan Roese /* last 2 lwords in OCRAM */ 93*ae9996c8SStefan Roese #define CONFIG_SYS_BOOTCOUNT_ADDR 0xfffffff8 94*ae9996c8SStefan Roese #define CONFIG_SYS_BOOTCOUNT_BE 95*ae9996c8SStefan Roese 96*ae9996c8SStefan Roese /* The rest of the configuration is shared */ 97*ae9996c8SStefan Roese #include <configs/socfpga_common.h> 98*ae9996c8SStefan Roese 99*ae9996c8SStefan Roese /* U-Boot payload is stored at offset 0x60000 */ 100*ae9996c8SStefan Roese #undef CONFIG_SYS_SPI_U_BOOT_OFFS 101*ae9996c8SStefan Roese #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x60000 102*ae9996c8SStefan Roese 103*ae9996c8SStefan Roese /* Environment setting for SPI flash */ 104*ae9996c8SStefan Roese #undef CONFIG_ENV_SIZE 105*ae9996c8SStefan Roese #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 106*ae9996c8SStefan Roese #define CONFIG_ENV_SECT_SIZE (64 * 1024) 107*ae9996c8SStefan Roese #define CONFIG_ENV_SIZE (16 * 1024) 108*ae9996c8SStefan Roese #define CONFIG_ENV_OFFSET 0x00040000 109*ae9996c8SStefan Roese #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) 110*ae9996c8SStefan Roese #define CONFIG_ENV_SPI_BUS 0 111*ae9996c8SStefan Roese #define CONFIG_ENV_SPI_CS 0 112*ae9996c8SStefan Roese #define CONFIG_ENV_SPI_MODE SPI_MODE_3 113*ae9996c8SStefan Roese #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 114*ae9996c8SStefan Roese 115*ae9996c8SStefan Roese #endif /* __CONFIG_SOCFPGA_SR1500_H__ */ 116