1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2ae9996c8SStefan Roese /* 3ae9996c8SStefan Roese * Copyright (C) 2015 Stefan Roese <sr@denx.de> 4ae9996c8SStefan Roese */ 5ae9996c8SStefan Roese #ifndef __CONFIG_SOCFPGA_SR1500_H__ 6ae9996c8SStefan Roese #define __CONFIG_SOCFPGA_SR1500_H__ 7ae9996c8SStefan Roese 8ae9996c8SStefan Roese #include <asm/arch/base_addr_ac5.h> 9ae9996c8SStefan Roese 10ae9996c8SStefan Roese /* Memory configurations */ 11ae9996c8SStefan Roese #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */ 12ae9996c8SStefan Roese 13ae9996c8SStefan Roese /* Booting Linux */ 14ae9996c8SStefan Roese #define CONFIG_LOADADDR 0x01000000 15ae9996c8SStefan Roese #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 16ae9996c8SStefan Roese 17ae9996c8SStefan Roese /* Ethernet on SoC (EMAC) */ 18ae9996c8SStefan Roese #define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII 19ae9996c8SStefan Roese /* The PHY is autodetected, so no MII PHY address is needed here */ 20ae9996c8SStefan Roese #define PHY_ANEG_TIMEOUT 8000 21ae9996c8SStefan Roese 22ae9996c8SStefan Roese /* Environment */ 23ae9996c8SStefan Roese 24ae9996c8SStefan Roese /* Enable SPI NOR flash reset, needed for SPI booting */ 25ae9996c8SStefan Roese #define CONFIG_SPI_N25Q256A_RESET 26ae9996c8SStefan Roese 27ae9996c8SStefan Roese /* 28ae9996c8SStefan Roese * Bootcounter 29ae9996c8SStefan Roese */ 30ae9996c8SStefan Roese #define CONFIG_SYS_BOOTCOUNT_BE 31ae9996c8SStefan Roese 32ae9996c8SStefan Roese /* Environment setting for SPI flash */ 33ae9996c8SStefan Roese #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 34ae9996c8SStefan Roese #define CONFIG_ENV_SECT_SIZE (64 * 1024) 35ae9996c8SStefan Roese #define CONFIG_ENV_SIZE (16 * 1024) 3693d9fc26SStefan Roese #define CONFIG_ENV_OFFSET 0x000e0000 37ae9996c8SStefan Roese #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) 3893d9fc26SStefan Roese 3993d9fc26SStefan Roese /* 4093d9fc26SStefan Roese * The QSPI NOR flash layout on SR1500: 4193d9fc26SStefan Roese * 4293d9fc26SStefan Roese * 0000.0000 - 0003.ffff: SPL (4 times) 4393d9fc26SStefan Roese * 0004.0000 - 000d.ffff: U-Boot 4493d9fc26SStefan Roese * 000e.0000 - 000e.ffff: env1 4593d9fc26SStefan Roese * 000f.0000 - 000f.ffff: env2 4693d9fc26SStefan Roese */ 47ae9996c8SStefan Roese 48b72041ccSMarek Vasut /* The rest of the configuration is shared */ 49b72041ccSMarek Vasut #include <configs/socfpga_common.h> 50b72041ccSMarek Vasut 51ae9996c8SStefan Roese #endif /* __CONFIG_SOCFPGA_SR1500_H__ */ 52