1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 26bd041f0SDalon Westergreen /* 36bd041f0SDalon Westergreen * Copyright (C) 2017, Intel Corporation 46bd041f0SDalon Westergreen */ 56bd041f0SDalon Westergreen #ifndef __CONFIG_TERASIC_DE10_H__ 66bd041f0SDalon Westergreen #define __CONFIG_TERASIC_DE10_H__ 76bd041f0SDalon Westergreen 86bd041f0SDalon Westergreen #include <asm/arch/base_addr_ac5.h> 96bd041f0SDalon Westergreen 106bd041f0SDalon Westergreen /* Memory configurations */ 116bd041f0SDalon Westergreen #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */ 126bd041f0SDalon Westergreen 136bd041f0SDalon Westergreen /* Booting Linux */ 146bd041f0SDalon Westergreen #define CONFIG_LOADADDR 0x01000000 156bd041f0SDalon Westergreen #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 166bd041f0SDalon Westergreen 176bd041f0SDalon Westergreen /* Ethernet on SoC (EMAC) */ 186bd041f0SDalon Westergreen 196bd041f0SDalon Westergreen /* The rest of the configuration is shared */ 206bd041f0SDalon Westergreen #include <configs/socfpga_common.h> 216bd041f0SDalon Westergreen 226bd041f0SDalon Westergreen #endif /* __CONFIG_TERASIC_DE10_H__ */ 23