1 /* 2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef __CONFIG_SOCFPGA_COMMON_H__ 7 #define __CONFIG_SOCFPGA_COMMON_H__ 8 9 /* Virtual target or real hardware */ 10 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET 11 12 /* 13 * High level configuration 14 */ 15 #define CONFIG_DISPLAY_BOARDINFO_LATE 16 #define CONFIG_CLOCKS 17 18 #define CONFIG_CRC32_VERIFY 19 20 #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) 21 22 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 23 24 /* add target to build it automatically upon "make" */ 25 #define CONFIG_BUILD_TARGET "u-boot-with-spl.sfp" 26 27 /* 28 * Memory configurations 29 */ 30 #define CONFIG_NR_DRAM_BANKS 1 31 #define PHYS_SDRAM_1 0x0 32 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) 33 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 34 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE 35 36 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 37 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 38 #define CONFIG_SYS_INIT_SP_OFFSET \ 39 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 40 #define CONFIG_SYS_INIT_SP_ADDR \ 41 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 42 43 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 44 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 45 #define CONFIG_SYS_TEXT_BASE 0x08000040 46 #else 47 #define CONFIG_SYS_TEXT_BASE 0x01000040 48 #endif 49 50 /* 51 * U-Boot general configurations 52 */ 53 #define CONFIG_SYS_LONGHELP 54 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ 55 #define CONFIG_SYS_PBSIZE \ 56 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 57 /* Print buffer size */ 58 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ 59 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 60 /* Boot argument buffer size */ 61 #define CONFIG_AUTO_COMPLETE /* Command auto complete */ 62 #define CONFIG_CMDLINE_EDITING /* Command history etc */ 63 64 #ifndef CONFIG_SYS_HOSTNAME 65 #define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD 66 #endif 67 68 /* 69 * Cache 70 */ 71 #define CONFIG_SYS_L2_PL310 72 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS 73 74 /* 75 * SDRAM controller 76 */ 77 #define CONFIG_ALTERA_SDRAM 78 79 /* 80 * EPCS/EPCQx1 Serial Flash Controller 81 */ 82 #ifdef CONFIG_ALTERA_SPI 83 #define CONFIG_SF_DEFAULT_SPEED 30000000 84 /* 85 * The base address is configurable in QSys, each board must specify the 86 * base address based on it's particular FPGA configuration. Please note 87 * that the address here is incremented by 0x400 from the Base address 88 * selected in QSys, since the SPI registers are at offset +0x400. 89 * #define CONFIG_SYS_SPI_BASE 0xff240400 90 */ 91 #endif 92 93 /* 94 * Ethernet on SoC (EMAC) 95 */ 96 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) 97 #define CONFIG_DW_ALTDESCRIPTOR 98 #define CONFIG_MII 99 #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) 100 #define CONFIG_PHY_GIGE 101 #endif 102 103 /* 104 * FPGA Driver 105 */ 106 #ifdef CONFIG_CMD_FPGA 107 #define CONFIG_FPGA 108 #define CONFIG_FPGA_ALTERA 109 #define CONFIG_FPGA_SOCFPGA 110 #define CONFIG_FPGA_COUNT 1 111 #endif 112 113 /* 114 * L4 OSC1 Timer 0 115 */ 116 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */ 117 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS 118 #define CONFIG_SYS_TIMER_COUNTS_DOWN 119 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) 120 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 121 #define CONFIG_SYS_TIMER_RATE 2400000 122 #else 123 #define CONFIG_SYS_TIMER_RATE 25000000 124 #endif 125 126 /* 127 * L4 Watchdog 128 */ 129 #ifdef CONFIG_HW_WATCHDOG 130 #define CONFIG_DESIGNWARE_WATCHDOG 131 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS 132 #define CONFIG_DW_WDT_CLOCK_KHZ 25000 133 #define CONFIG_HW_WATCHDOG_TIMEOUT_MS 30000 134 #endif 135 136 /* 137 * MMC Driver 138 */ 139 #ifdef CONFIG_CMD_MMC 140 #define CONFIG_BOUNCE_BUFFER 141 /* FIXME */ 142 /* using smaller max blk cnt to avoid flooding the limited stack we have */ 143 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ 144 #endif 145 146 /* 147 * NAND Support 148 */ 149 #ifdef CONFIG_NAND_DENALI 150 #define CONFIG_SYS_MAX_NAND_DEVICE 1 151 #define CONFIG_SYS_NAND_MAX_CHIPS 1 152 #define CONFIG_SYS_NAND_ONFI_DETECTION 153 #define CONFIG_NAND_DENALI_ECC_SIZE 512 154 #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS 155 #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS 156 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) 157 #endif 158 159 /* 160 * I2C support 161 */ 162 #define CONFIG_SYS_I2C 163 #define CONFIG_SYS_I2C_BUS_MAX 4 164 #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS 165 #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS 166 #define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS 167 #define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS 168 /* Using standard mode which the speed up to 100Kb/s */ 169 #define CONFIG_SYS_I2C_SPEED 100000 170 #define CONFIG_SYS_I2C_SPEED1 100000 171 #define CONFIG_SYS_I2C_SPEED2 100000 172 #define CONFIG_SYS_I2C_SPEED3 100000 173 /* Address of device when used as slave */ 174 #define CONFIG_SYS_I2C_SLAVE 0x02 175 #define CONFIG_SYS_I2C_SLAVE1 0x02 176 #define CONFIG_SYS_I2C_SLAVE2 0x02 177 #define CONFIG_SYS_I2C_SLAVE3 0x02 178 #ifndef __ASSEMBLY__ 179 /* Clock supplied to I2C controller in unit of MHz */ 180 unsigned int cm_get_l4_sp_clk_hz(void); 181 #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000) 182 #endif 183 184 /* 185 * QSPI support 186 */ 187 /* Enable multiple SPI NOR flash manufacturers */ 188 #ifndef CONFIG_SPL_BUILD 189 #define CONFIG_SPI_FLASH_MTD 190 #define CONFIG_CMD_MTDPARTS 191 #define CONFIG_MTD_DEVICE 192 #define CONFIG_MTD_PARTITIONS 193 #define MTDIDS_DEFAULT "nor0=ff705000.spi.0" 194 #endif 195 /* QSPI reference clock */ 196 #ifndef __ASSEMBLY__ 197 unsigned int cm_get_qspi_controller_clk_hz(void); 198 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() 199 #endif 200 #define CONFIG_CQSPI_DECODER 0 201 #define CONFIG_BOUNCE_BUFFER 202 203 /* 204 * Designware SPI support 205 */ 206 207 /* 208 * Serial Driver 209 */ 210 #define CONFIG_SYS_NS16550_SERIAL 211 #define CONFIG_SYS_NS16550_REG_SIZE -4 212 #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS 213 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 214 #define CONFIG_SYS_NS16550_CLK 1000000 215 #else 216 #define CONFIG_SYS_NS16550_CLK 100000000 217 #endif 218 #define CONFIG_CONS_INDEX 1 219 220 /* 221 * USB 222 */ 223 #ifdef CONFIG_CMD_USB 224 #define CONFIG_USB_DWC2 225 #endif 226 227 /* 228 * USB Gadget (DFU, UMS) 229 */ 230 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) 231 #define CONFIG_USB_FUNCTION_MASS_STORAGE 232 233 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024) 234 #define DFU_DEFAULT_POLL_TIMEOUT 300 235 236 /* USB IDs */ 237 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 238 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 239 #endif 240 241 /* 242 * U-Boot environment 243 */ 244 #if !defined(CONFIG_ENV_SIZE) 245 #define CONFIG_ENV_SIZE 4096 246 #endif 247 248 /* Environment for SDMMC boot */ 249 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET) 250 #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ 251 #define CONFIG_ENV_OFFSET 512 /* just after the MBR */ 252 #endif 253 254 /* Environment for QSPI boot */ 255 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET) 256 #define CONFIG_ENV_OFFSET 0x00100000 257 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 258 #endif 259 260 /* 261 * mtd partitioning for serial NOR flash 262 * 263 * device nor0 <ff705000.spi.0>, # parts = 6 264 * #: name size offset mask_flags 265 * 0: u-boot 0x00100000 0x00000000 0 266 * 1: env1 0x00040000 0x00100000 0 267 * 2: env2 0x00040000 0x00140000 0 268 * 3: UBI 0x03e80000 0x00180000 0 269 * 4: boot 0x00e80000 0x00180000 0 270 * 5: rootfs 0x01000000 0x01000000 0 271 * 272 */ 273 #if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT) 274 #define MTDPARTS_DEFAULT "mtdparts=ff705000.spi.0:"\ 275 "1m(u-boot)," \ 276 "256k(env1)," \ 277 "256k(env2)," \ 278 "14848k(boot)," \ 279 "16m(rootfs)," \ 280 "-@1536k(UBI)\0" 281 #endif 282 283 /* UBI and UBIFS support */ 284 #if defined(CONFIG_CMD_SF) || defined(CONFIG_CMD_NAND) 285 #define CONFIG_CMD_UBIFS 286 #define CONFIG_RBTREE 287 #define CONFIG_LZO 288 #endif 289 290 /* 291 * SPL 292 * 293 * SRAM Memory layout: 294 * 295 * 0xFFFF_0000 ...... Start of SRAM 296 * 0xFFFF_xxxx ...... Top of stack (grows down) 297 * 0xFFFF_yyyy ...... Malloc area 298 * 0xFFFF_zzzz ...... Global Data 299 * 0xFFFF_FF00 ...... End of SRAM 300 */ 301 #define CONFIG_SPL_FRAMEWORK 302 #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR 303 #define CONFIG_SPL_MAX_SIZE (64 * 1024) 304 305 /* SPL SDMMC boot support */ 306 #ifdef CONFIG_SPL_MMC_SUPPORT 307 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) 308 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 2 309 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" 310 #endif 311 #endif 312 313 /* SPL QSPI boot support */ 314 #ifdef CONFIG_SPL_SPI_SUPPORT 315 #define CONFIG_SPL_SPI_LOAD 316 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 317 #endif 318 319 /* SPL NAND boot support */ 320 #ifdef CONFIG_SPL_NAND_SUPPORT 321 #define CONFIG_SYS_NAND_USE_FLASH_BBT 322 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 323 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 324 #endif 325 326 /* 327 * Stack setup 328 */ 329 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR 330 331 #endif /* __CONFIG_SOCFPGA_COMMON_H__ */ 332