1 /* 2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef __CONFIG_SOCFPGA_COMMON_H__ 7 #define __CONFIG_SOCFPGA_COMMON_H__ 8 9 /* Virtual target or real hardware */ 10 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET 11 12 /* 13 * High level configuration 14 */ 15 #define CONFIG_DISPLAY_BOARDINFO_LATE 16 #define CONFIG_CLOCKS 17 18 #define CONFIG_CRC32_VERIFY 19 20 #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) 21 22 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 23 24 /* add target to build it automatically upon "make" */ 25 #define CONFIG_BUILD_TARGET "u-boot-with-spl.sfp" 26 27 /* 28 * Memory configurations 29 */ 30 #define CONFIG_NR_DRAM_BANKS 1 31 #define PHYS_SDRAM_1 0x0 32 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) 33 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 34 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE 35 #if defined(CONFIG_TARGET_SOCFPGA_GEN5) 36 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 37 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 38 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 39 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 40 #define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */ 41 #endif 42 #define CONFIG_SYS_INIT_SP_OFFSET \ 43 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 44 #define CONFIG_SYS_INIT_SP_ADDR \ 45 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 46 47 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 48 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 49 #define CONFIG_SYS_TEXT_BASE 0x08000040 50 #else 51 #define CONFIG_SYS_TEXT_BASE 0x01000040 52 #endif 53 54 /* 55 * U-Boot general configurations 56 */ 57 #define CONFIG_SYS_LONGHELP 58 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ 59 #define CONFIG_SYS_PBSIZE \ 60 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 61 /* Print buffer size */ 62 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ 63 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 64 /* Boot argument buffer size */ 65 #define CONFIG_AUTO_COMPLETE /* Command auto complete */ 66 #define CONFIG_CMDLINE_EDITING /* Command history etc */ 67 68 #ifndef CONFIG_SYS_HOSTNAME 69 #define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD 70 #endif 71 72 #define CONFIG_CMD_PXE 73 #define CONFIG_MENU 74 75 /* 76 * Cache 77 */ 78 #define CONFIG_SYS_L2_PL310 79 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS 80 81 /* 82 * EPCS/EPCQx1 Serial Flash Controller 83 */ 84 #ifdef CONFIG_ALTERA_SPI 85 #define CONFIG_SF_DEFAULT_SPEED 30000000 86 /* 87 * The base address is configurable in QSys, each board must specify the 88 * base address based on it's particular FPGA configuration. Please note 89 * that the address here is incremented by 0x400 from the Base address 90 * selected in QSys, since the SPI registers are at offset +0x400. 91 * #define CONFIG_SYS_SPI_BASE 0xff240400 92 */ 93 #endif 94 95 /* 96 * Ethernet on SoC (EMAC) 97 */ 98 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) 99 #define CONFIG_DW_ALTDESCRIPTOR 100 #define CONFIG_MII 101 #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) 102 #define CONFIG_PHY_GIGE 103 #endif 104 105 /* 106 * FPGA Driver 107 */ 108 #ifdef CONFIG_TARGET_SOCFPGA_GEN5 109 #ifdef CONFIG_CMD_FPGA 110 #define CONFIG_FPGA 111 #define CONFIG_FPGA_ALTERA 112 #define CONFIG_FPGA_SOCFPGA 113 #define CONFIG_FPGA_COUNT 1 114 #endif 115 #endif 116 /* 117 * L4 OSC1 Timer 0 118 */ 119 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */ 120 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS 121 #define CONFIG_SYS_TIMER_COUNTS_DOWN 122 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) 123 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 124 #define CONFIG_SYS_TIMER_RATE 2400000 125 #else 126 #define CONFIG_SYS_TIMER_RATE 25000000 127 #endif 128 129 /* 130 * L4 Watchdog 131 */ 132 #ifdef CONFIG_HW_WATCHDOG 133 #define CONFIG_DESIGNWARE_WATCHDOG 134 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS 135 #define CONFIG_DW_WDT_CLOCK_KHZ 25000 136 #define CONFIG_HW_WATCHDOG_TIMEOUT_MS 30000 137 #endif 138 139 /* 140 * MMC Driver 141 */ 142 #ifdef CONFIG_CMD_MMC 143 #define CONFIG_BOUNCE_BUFFER 144 /* FIXME */ 145 /* using smaller max blk cnt to avoid flooding the limited stack we have */ 146 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ 147 #endif 148 149 /* 150 * NAND Support 151 */ 152 #ifdef CONFIG_NAND_DENALI 153 #define CONFIG_SYS_MAX_NAND_DEVICE 1 154 #define CONFIG_SYS_NAND_MAX_CHIPS 1 155 #define CONFIG_SYS_NAND_ONFI_DETECTION 156 #define CONFIG_NAND_DENALI_ECC_SIZE 512 157 #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS 158 #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS 159 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) 160 #endif 161 162 /* 163 * I2C support 164 */ 165 #define CONFIG_SYS_I2C 166 #define CONFIG_SYS_I2C_BUS_MAX 4 167 #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS 168 #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS 169 #define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS 170 #define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS 171 /* Using standard mode which the speed up to 100Kb/s */ 172 #define CONFIG_SYS_I2C_SPEED 100000 173 #define CONFIG_SYS_I2C_SPEED1 100000 174 #define CONFIG_SYS_I2C_SPEED2 100000 175 #define CONFIG_SYS_I2C_SPEED3 100000 176 /* Address of device when used as slave */ 177 #define CONFIG_SYS_I2C_SLAVE 0x02 178 #define CONFIG_SYS_I2C_SLAVE1 0x02 179 #define CONFIG_SYS_I2C_SLAVE2 0x02 180 #define CONFIG_SYS_I2C_SLAVE3 0x02 181 #ifndef __ASSEMBLY__ 182 /* Clock supplied to I2C controller in unit of MHz */ 183 unsigned int cm_get_l4_sp_clk_hz(void); 184 #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000) 185 #endif 186 187 /* 188 * QSPI support 189 */ 190 /* Enable multiple SPI NOR flash manufacturers */ 191 #ifndef CONFIG_SPL_BUILD 192 #define CONFIG_SPI_FLASH_MTD 193 #define CONFIG_CMD_MTDPARTS 194 #define CONFIG_MTD_DEVICE 195 #define CONFIG_MTD_PARTITIONS 196 #define MTDIDS_DEFAULT "nor0=ff705000.spi.0" 197 #endif 198 /* QSPI reference clock */ 199 #ifndef __ASSEMBLY__ 200 unsigned int cm_get_qspi_controller_clk_hz(void); 201 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() 202 #endif 203 #define CONFIG_CQSPI_DECODER 0 204 #define CONFIG_BOUNCE_BUFFER 205 206 /* 207 * Designware SPI support 208 */ 209 210 /* 211 * Serial Driver 212 */ 213 #define CONFIG_SYS_NS16550_SERIAL 214 #define CONFIG_SYS_NS16550_REG_SIZE -4 215 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 216 #define CONFIG_SYS_NS16550_CLK 1000000 217 #elif defined(CONFIG_TARGET_SOCFPGA_GEN5) 218 #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS 219 #define CONFIG_SYS_NS16550_CLK 100000000 220 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 221 #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART1_ADDRESS 222 #define CONFIG_SYS_NS16550_CLK 50000000 223 #endif 224 #define CONFIG_CONS_INDEX 1 225 226 /* 227 * USB 228 */ 229 #ifdef CONFIG_CMD_USB 230 #define CONFIG_USB_DWC2 231 #endif 232 233 /* 234 * USB Gadget (DFU, UMS) 235 */ 236 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) 237 #define CONFIG_USB_FUNCTION_MASS_STORAGE 238 239 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024) 240 #define DFU_DEFAULT_POLL_TIMEOUT 300 241 242 /* USB IDs */ 243 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 244 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 245 #endif 246 247 /* 248 * U-Boot environment 249 */ 250 #if !defined(CONFIG_ENV_SIZE) 251 #define CONFIG_ENV_SIZE (8 * 1024) 252 #endif 253 254 /* Environment for SDMMC boot */ 255 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET) 256 #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ 257 #define CONFIG_ENV_OFFSET (34 * 512) /* just after the GPT */ 258 #endif 259 260 /* Environment for QSPI boot */ 261 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET) 262 #define CONFIG_ENV_OFFSET 0x00100000 263 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 264 #endif 265 266 /* 267 * mtd partitioning for serial NOR flash 268 * 269 * device nor0 <ff705000.spi.0>, # parts = 6 270 * #: name size offset mask_flags 271 * 0: u-boot 0x00100000 0x00000000 0 272 * 1: env1 0x00040000 0x00100000 0 273 * 2: env2 0x00040000 0x00140000 0 274 * 3: UBI 0x03e80000 0x00180000 0 275 * 4: boot 0x00e80000 0x00180000 0 276 * 5: rootfs 0x01000000 0x01000000 0 277 * 278 */ 279 #if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT) 280 #define MTDPARTS_DEFAULT "mtdparts=ff705000.spi.0:"\ 281 "1m(u-boot)," \ 282 "256k(env1)," \ 283 "256k(env2)," \ 284 "14848k(boot)," \ 285 "16m(rootfs)," \ 286 "-@1536k(UBI)\0" 287 #endif 288 289 /* UBI and UBIFS support */ 290 #if defined(CONFIG_CMD_SF) || defined(CONFIG_CMD_NAND) 291 #define CONFIG_CMD_UBIFS 292 #define CONFIG_RBTREE 293 #define CONFIG_LZO 294 #endif 295 296 /* 297 * SPL 298 * 299 * SRAM Memory layout: 300 * 301 * 0xFFFF_0000 ...... Start of SRAM 302 * 0xFFFF_xxxx ...... Top of stack (grows down) 303 * 0xFFFF_yyyy ...... Malloc area 304 * 0xFFFF_zzzz ...... Global Data 305 * 0xFFFF_FF00 ...... End of SRAM 306 */ 307 #define CONFIG_SPL_FRAMEWORK 308 #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR 309 #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE 310 311 /* SPL SDMMC boot support */ 312 #ifdef CONFIG_SPL_MMC_SUPPORT 313 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) 314 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" 315 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 316 #endif 317 #else 318 #ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 319 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 320 #endif 321 #endif 322 323 /* SPL QSPI boot support */ 324 #ifdef CONFIG_SPL_SPI_SUPPORT 325 #define CONFIG_SPL_SPI_LOAD 326 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 327 #endif 328 329 /* SPL NAND boot support */ 330 #ifdef CONFIG_SPL_NAND_SUPPORT 331 #define CONFIG_SYS_NAND_USE_FLASH_BBT 332 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 333 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 334 #endif 335 336 /* 337 * Stack setup 338 */ 339 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR 340 341 /* Extra Environment */ 342 #ifndef CONFIG_SPL_BUILD 343 #include <config_distro_defaults.h> 344 345 #ifdef CONFIG_CMD_PXE 346 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) 347 #else 348 #define BOOT_TARGET_DEVICES_PXE(func) 349 #endif 350 351 #ifdef CONFIG_CMD_MMC 352 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) 353 #else 354 #define BOOT_TARGET_DEVICES_MMC(func) 355 #endif 356 357 #define BOOT_TARGET_DEVICES(func) \ 358 BOOT_TARGET_DEVICES_MMC(func) \ 359 BOOT_TARGET_DEVICES_PXE(func) \ 360 func(DHCP, dhcp, na) 361 362 #include <config_distro_bootcmd.h> 363 364 #ifndef CONFIG_EXTRA_ENV_SETTINGS 365 #define CONFIG_EXTRA_ENV_SETTINGS \ 366 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ 367 "bootm_size=0xa000000\0" \ 368 "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ 369 "fdt_addr_r=0x02000000\0" \ 370 "scriptaddr=0x02100000\0" \ 371 "pxefile_addr_r=0x02200000\0" \ 372 "ramdisk_addr_r=0x02300000\0" \ 373 BOOTENV 374 375 #endif 376 #endif 377 378 #endif /* __CONFIG_SOCFPGA_COMMON_H__ */ 379