1 /* 2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ 7 #define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ 8 9 10 /* Virtual target or real hardware */ 11 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET 12 13 #define CONFIG_SYS_THUMB_BUILD 14 15 /* 16 * High level configuration 17 */ 18 #define CONFIG_DISPLAY_CPUINFO 19 #define CONFIG_DISPLAY_BOARDINFO_LATE 20 #define CONFIG_ARCH_MISC_INIT 21 #define CONFIG_ARCH_EARLY_INIT_R 22 #define CONFIG_SYS_NO_FLASH 23 #define CONFIG_CLOCKS 24 25 #define CONFIG_CRC32_VERIFY 26 27 #define CONFIG_FIT 28 #define CONFIG_OF_LIBFDT 29 #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) 30 31 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 32 33 /* 34 * Memory configurations 35 */ 36 #define CONFIG_NR_DRAM_BANKS 1 37 #define PHYS_SDRAM_1 0x0 38 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) 39 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 40 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE 41 42 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 43 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 44 #define CONFIG_SYS_INIT_SP_OFFSET \ 45 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 46 #define CONFIG_SYS_INIT_SP_ADDR \ 47 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 48 49 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 50 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 51 #define CONFIG_SYS_TEXT_BASE 0x08000040 52 #else 53 #define CONFIG_SYS_TEXT_BASE 0x01000040 54 #endif 55 56 /* 57 * U-Boot general configurations 58 */ 59 #define CONFIG_SYS_LONGHELP 60 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ 61 #define CONFIG_SYS_PBSIZE \ 62 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 63 /* Print buffer size */ 64 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ 65 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 66 /* Boot argument buffer size */ 67 #define CONFIG_VERSION_VARIABLE /* U-BOOT version */ 68 #define CONFIG_AUTO_COMPLETE /* Command auto complete */ 69 #define CONFIG_CMDLINE_EDITING /* Command history etc */ 70 #define CONFIG_SYS_HUSH_PARSER 71 72 #ifndef CONFIG_SYS_HOSTNAME 73 #define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD 74 #endif 75 76 /* 77 * Cache 78 */ 79 #define CONFIG_SYS_CACHELINE_SIZE 32 80 #define CONFIG_SYS_L2_PL310 81 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS 82 83 /* 84 * SDRAM controller 85 */ 86 #define CONFIG_ALTERA_SDRAM 87 88 /* 89 * EPCS/EPCQx1 Serial Flash Controller 90 */ 91 #ifdef CONFIG_ALTERA_SPI 92 #define CONFIG_CMD_SPI 93 #define CONFIG_CMD_SF 94 #define CONFIG_SF_DEFAULT_SPEED 30000000 95 #define CONFIG_SPI_FLASH_BAR 96 /* 97 * The base address is configurable in QSys, each board must specify the 98 * base address based on it's particular FPGA configuration. Please note 99 * that the address here is incremented by 0x400 from the Base address 100 * selected in QSys, since the SPI registers are at offset +0x400. 101 * #define CONFIG_SYS_SPI_BASE 0xff240400 102 */ 103 #endif 104 105 /* 106 * Ethernet on SoC (EMAC) 107 */ 108 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) 109 #define CONFIG_DW_ALTDESCRIPTOR 110 #define CONFIG_MII 111 #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) 112 #define CONFIG_PHYLIB 113 #define CONFIG_PHY_GIGE 114 #endif 115 116 /* 117 * FPGA Driver 118 */ 119 #ifdef CONFIG_CMD_FPGA 120 #define CONFIG_FPGA 121 #define CONFIG_FPGA_ALTERA 122 #define CONFIG_FPGA_SOCFPGA 123 #define CONFIG_FPGA_COUNT 1 124 #endif 125 126 /* 127 * L4 OSC1 Timer 0 128 */ 129 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */ 130 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS 131 #define CONFIG_SYS_TIMER_COUNTS_DOWN 132 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) 133 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 134 #define CONFIG_SYS_TIMER_RATE 2400000 135 #else 136 #define CONFIG_SYS_TIMER_RATE 25000000 137 #endif 138 139 /* 140 * L4 Watchdog 141 */ 142 #ifdef CONFIG_HW_WATCHDOG 143 #define CONFIG_DESIGNWARE_WATCHDOG 144 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS 145 #define CONFIG_DW_WDT_CLOCK_KHZ 25000 146 #define CONFIG_HW_WATCHDOG_TIMEOUT_MS 30000 147 #endif 148 149 /* 150 * MMC Driver 151 */ 152 #ifdef CONFIG_CMD_MMC 153 #define CONFIG_MMC 154 #define CONFIG_BOUNCE_BUFFER 155 #define CONFIG_GENERIC_MMC 156 #define CONFIG_DWMMC 157 #define CONFIG_SOCFPGA_DWMMC 158 #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024 159 /* FIXME */ 160 /* using smaller max blk cnt to avoid flooding the limited stack we have */ 161 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ 162 #endif 163 164 /* 165 * I2C support 166 */ 167 #define CONFIG_SYS_I2C 168 #define CONFIG_SYS_I2C_DW 169 #define CONFIG_SYS_I2C_BUS_MAX 4 170 #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS 171 #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS 172 #define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS 173 #define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS 174 /* Using standard mode which the speed up to 100Kb/s */ 175 #define CONFIG_SYS_I2C_SPEED 100000 176 #define CONFIG_SYS_I2C_SPEED1 100000 177 #define CONFIG_SYS_I2C_SPEED2 100000 178 #define CONFIG_SYS_I2C_SPEED3 100000 179 /* Address of device when used as slave */ 180 #define CONFIG_SYS_I2C_SLAVE 0x02 181 #define CONFIG_SYS_I2C_SLAVE1 0x02 182 #define CONFIG_SYS_I2C_SLAVE2 0x02 183 #define CONFIG_SYS_I2C_SLAVE3 0x02 184 #ifndef __ASSEMBLY__ 185 /* Clock supplied to I2C controller in unit of MHz */ 186 unsigned int cm_get_l4_sp_clk_hz(void); 187 #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000) 188 #endif 189 #define CONFIG_CMD_I2C 190 191 /* 192 * QSPI support 193 */ 194 /* Enable multiple SPI NOR flash manufacturers */ 195 #ifndef CONFIG_SPL_BUILD 196 #define CONFIG_SPI_FLASH_MTD 197 #define CONFIG_CMD_MTDPARTS 198 #define CONFIG_MTD_DEVICE 199 #define CONFIG_MTD_PARTITIONS 200 #define MTDIDS_DEFAULT "nor0=ff705000.spi" 201 #endif 202 /* QSPI reference clock */ 203 #ifndef __ASSEMBLY__ 204 unsigned int cm_get_qspi_controller_clk_hz(void); 205 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() 206 #endif 207 #define CONFIG_CQSPI_DECODER 0 208 #define CONFIG_CMD_SF 209 #define CONFIG_SPI_FLASH_BAR 210 211 /* 212 * Designware SPI support 213 */ 214 #define CONFIG_CMD_SPI 215 216 /* 217 * Serial Driver 218 */ 219 #define CONFIG_SYS_NS16550_SERIAL 220 #define CONFIG_SYS_NS16550_REG_SIZE -4 221 #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS 222 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 223 #define CONFIG_SYS_NS16550_CLK 1000000 224 #else 225 #define CONFIG_SYS_NS16550_CLK 100000000 226 #endif 227 #define CONFIG_CONS_INDEX 1 228 #define CONFIG_BAUDRATE 115200 229 230 /* 231 * USB 232 */ 233 #ifdef CONFIG_CMD_USB 234 #define CONFIG_USB_DWC2 235 #define CONFIG_USB_STORAGE 236 /* 237 * NOTE: User must define either of the following to select which 238 * of the two USB controllers available on SoCFPGA to use. 239 * The DWC2 driver doesn't support multiple USB controllers. 240 * #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB0_ADDRESS 241 * #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS 242 */ 243 #endif 244 245 /* 246 * USB Gadget (DFU, UMS) 247 */ 248 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) 249 #define CONFIG_USB_GADGET 250 #define CONFIG_USB_GADGET_DWC2_OTG 251 #define CONFIG_USB_GADGET_DUALSPEED 252 #define CONFIG_USB_GADGET_VBUS_DRAW 2 253 254 /* USB Composite download gadget - g_dnl */ 255 #define CONFIG_USB_GADGET_DOWNLOAD 256 #define CONFIG_USB_FUNCTION_MASS_STORAGE 257 258 #define CONFIG_USB_FUNCTION_DFU 259 #define CONFIG_DFU_MMC 260 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024) 261 #define DFU_DEFAULT_POLL_TIMEOUT 300 262 263 /* USB IDs */ 264 #define CONFIG_G_DNL_VENDOR_NUM 0x0525 /* NetChip */ 265 #define CONFIG_G_DNL_PRODUCT_NUM 0xA4A5 /* Linux-USB File-backed Storage Gadget */ 266 #define CONFIG_G_DNL_UMS_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM 267 #define CONFIG_G_DNL_UMS_PRODUCT_NUM CONFIG_G_DNL_PRODUCT_NUM 268 #ifndef CONFIG_G_DNL_MANUFACTURER 269 #define CONFIG_G_DNL_MANUFACTURER CONFIG_SYS_VENDOR 270 #endif 271 #endif 272 273 /* 274 * U-Boot environment 275 */ 276 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 277 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 278 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 279 #define CONFIG_ENV_SIZE 4096 280 281 /* 282 * SPL 283 * 284 * SRAM Memory layout: 285 * 286 * 0xFFFF_0000 ...... Start of SRAM 287 * 0xFFFF_xxxx ...... Top of stack (grows down) 288 * 0xFFFF_yyyy ...... Malloc area 289 * 0xFFFF_zzzz ...... Global Data 290 * 0xFFFF_FF00 ...... End of SRAM 291 */ 292 #define CONFIG_SPL_FRAMEWORK 293 #define CONFIG_SPL_RAM_DEVICE 294 #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR 295 #define CONFIG_SPL_MAX_SIZE (64 * 1024) 296 #ifdef CONFIG_SPL_BUILD 297 #define CONFIG_SYS_MALLOC_SIMPLE 298 #endif 299 300 #define CONFIG_SPL_LIBCOMMON_SUPPORT 301 #define CONFIG_SPL_LIBGENERIC_SUPPORT 302 #define CONFIG_SPL_WATCHDOG_SUPPORT 303 #define CONFIG_SPL_SERIAL_SUPPORT 304 #define CONFIG_SPL_MMC_SUPPORT 305 #define CONFIG_SPL_SPI_SUPPORT 306 307 /* SPL SDMMC boot support */ 308 #ifdef CONFIG_SPL_MMC_SUPPORT 309 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) 310 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 2 311 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" 312 #define CONFIG_SPL_LIBDISK_SUPPORT 313 #else 314 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 3 315 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xa00 /* offset 2560 sect (1M+256k) */ 316 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */ 317 #endif 318 #endif 319 320 /* SPL QSPI boot support */ 321 #ifdef CONFIG_SPL_SPI_SUPPORT 322 #define CONFIG_DM_SEQ_ALIAS 1 323 #define CONFIG_SPL_SPI_FLASH_SUPPORT 324 #define CONFIG_SPL_SPI_LOAD 325 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 326 #endif 327 328 /* 329 * Stack setup 330 */ 331 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR 332 333 #endif /* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */ 334