1 /* 2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef __CONFIG_SOCFPGA_COMMON_H__ 7 #define __CONFIG_SOCFPGA_COMMON_H__ 8 9 /* Virtual target or real hardware */ 10 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET 11 12 /* 13 * High level configuration 14 */ 15 #define CONFIG_CLOCKS 16 17 #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) 18 19 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 20 21 /* add target to build it automatically upon "make" */ 22 #define CONFIG_BUILD_TARGET "u-boot-with-spl.sfp" 23 24 /* 25 * Memory configurations 26 */ 27 #define CONFIG_NR_DRAM_BANKS 1 28 #define PHYS_SDRAM_1 0x0 29 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) 30 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 31 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE 32 #if defined(CONFIG_TARGET_SOCFPGA_GEN5) 33 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 34 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 35 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 36 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 37 #define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */ 38 #endif 39 #define CONFIG_SYS_INIT_SP_OFFSET \ 40 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 41 #define CONFIG_SYS_INIT_SP_ADDR \ 42 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 43 44 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 45 46 /* 47 * U-Boot general configurations 48 */ 49 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ 50 /* Print buffer size */ 51 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ 52 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 53 /* Boot argument buffer size */ 54 55 #ifndef CONFIG_SYS_HOSTNAME 56 #define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD 57 #endif 58 59 /* 60 * Cache 61 */ 62 #define CONFIG_SYS_L2_PL310 63 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS 64 65 /* 66 * EPCS/EPCQx1 Serial Flash Controller 67 */ 68 #ifdef CONFIG_ALTERA_SPI 69 #define CONFIG_SF_DEFAULT_SPEED 30000000 70 /* 71 * The base address is configurable in QSys, each board must specify the 72 * base address based on it's particular FPGA configuration. Please note 73 * that the address here is incremented by 0x400 from the Base address 74 * selected in QSys, since the SPI registers are at offset +0x400. 75 * #define CONFIG_SYS_SPI_BASE 0xff240400 76 */ 77 #endif 78 79 /* 80 * Ethernet on SoC (EMAC) 81 */ 82 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) 83 #define CONFIG_DW_ALTDESCRIPTOR 84 #define CONFIG_MII 85 #endif 86 87 /* 88 * FPGA Driver 89 */ 90 #ifdef CONFIG_CMD_FPGA 91 #define CONFIG_FPGA_COUNT 1 92 #endif 93 94 /* 95 * L4 OSC1 Timer 0 96 */ 97 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */ 98 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS 99 #define CONFIG_SYS_TIMER_COUNTS_DOWN 100 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) 101 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 102 #define CONFIG_SYS_TIMER_RATE 2400000 103 #else 104 #define CONFIG_SYS_TIMER_RATE 25000000 105 #endif 106 107 /* 108 * L4 Watchdog 109 */ 110 #ifdef CONFIG_HW_WATCHDOG 111 #define CONFIG_DESIGNWARE_WATCHDOG 112 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS 113 #define CONFIG_DW_WDT_CLOCK_KHZ 25000 114 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 30000 115 #endif 116 117 /* 118 * MMC Driver 119 */ 120 #ifdef CONFIG_CMD_MMC 121 #define CONFIG_BOUNCE_BUFFER 122 /* FIXME */ 123 /* using smaller max blk cnt to avoid flooding the limited stack we have */ 124 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ 125 #endif 126 127 /* 128 * NAND Support 129 */ 130 #ifdef CONFIG_NAND_DENALI 131 #define CONFIG_SYS_MAX_NAND_DEVICE 1 132 #define CONFIG_SYS_NAND_ONFI_DETECTION 133 #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS 134 #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS 135 #endif 136 137 /* 138 * I2C support 139 */ 140 #define CONFIG_SYS_I2C 141 #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS 142 #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS 143 #define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS 144 #define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS 145 /* Using standard mode which the speed up to 100Kb/s */ 146 #define CONFIG_SYS_I2C_SPEED 100000 147 #define CONFIG_SYS_I2C_SPEED1 100000 148 #define CONFIG_SYS_I2C_SPEED2 100000 149 #define CONFIG_SYS_I2C_SPEED3 100000 150 /* Address of device when used as slave */ 151 #define CONFIG_SYS_I2C_SLAVE 0x02 152 #define CONFIG_SYS_I2C_SLAVE1 0x02 153 #define CONFIG_SYS_I2C_SLAVE2 0x02 154 #define CONFIG_SYS_I2C_SLAVE3 0x02 155 #ifndef __ASSEMBLY__ 156 /* Clock supplied to I2C controller in unit of MHz */ 157 unsigned int cm_get_l4_sp_clk_hz(void); 158 #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000) 159 #endif 160 161 /* 162 * QSPI support 163 */ 164 /* Enable multiple SPI NOR flash manufacturers */ 165 #ifndef CONFIG_SPL_BUILD 166 #define CONFIG_SPI_FLASH_MTD 167 #define CONFIG_MTD_DEVICE 168 #define CONFIG_MTD_PARTITIONS 169 #endif 170 /* QSPI reference clock */ 171 #ifndef __ASSEMBLY__ 172 unsigned int cm_get_qspi_controller_clk_hz(void); 173 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() 174 #endif 175 176 /* 177 * Designware SPI support 178 */ 179 180 /* 181 * Serial Driver 182 */ 183 #define CONFIG_SYS_NS16550_SERIAL 184 #define CONFIG_SYS_NS16550_REG_SIZE -4 185 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 186 #define CONFIG_SYS_NS16550_CLK 1000000 187 #elif defined(CONFIG_TARGET_SOCFPGA_GEN5) 188 #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS 189 #define CONFIG_SYS_NS16550_CLK 100000000 190 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 191 #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART1_ADDRESS 192 #define CONFIG_SYS_NS16550_CLK 50000000 193 #endif 194 195 /* 196 * USB 197 */ 198 199 /* 200 * USB Gadget (DFU, UMS) 201 */ 202 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) 203 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024) 204 #define DFU_DEFAULT_POLL_TIMEOUT 300 205 206 /* USB IDs */ 207 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 208 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 209 #endif 210 211 /* 212 * U-Boot environment 213 */ 214 #if !defined(CONFIG_ENV_SIZE) 215 #define CONFIG_ENV_SIZE (8 * 1024) 216 #endif 217 218 /* Environment for SDMMC boot */ 219 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET) 220 #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ 221 #define CONFIG_ENV_OFFSET (34 * 512) /* just after the GPT */ 222 #endif 223 224 /* Environment for QSPI boot */ 225 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET) 226 #define CONFIG_ENV_OFFSET 0x00100000 227 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 228 #endif 229 230 /* 231 * mtd partitioning for serial NOR flash 232 * 233 * device nor0 <ff705000.spi.0>, # parts = 6 234 * #: name size offset mask_flags 235 * 0: u-boot 0x00100000 0x00000000 0 236 * 1: env1 0x00040000 0x00100000 0 237 * 2: env2 0x00040000 0x00140000 0 238 * 3: UBI 0x03e80000 0x00180000 0 239 * 4: boot 0x00e80000 0x00180000 0 240 * 5: rootfs 0x01000000 0x01000000 0 241 * 242 */ 243 244 /* 245 * SPL 246 * 247 * SRAM Memory layout: 248 * 249 * 0xFFFF_0000 ...... Start of SRAM 250 * 0xFFFF_xxxx ...... Top of stack (grows down) 251 * 0xFFFF_yyyy ...... Malloc area 252 * 0xFFFF_zzzz ...... Global Data 253 * 0xFFFF_FF00 ...... End of SRAM 254 */ 255 #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR 256 #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE 257 258 /* SPL SDMMC boot support */ 259 #ifdef CONFIG_SPL_MMC_SUPPORT 260 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) 261 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" 262 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 263 #endif 264 #else 265 #ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 266 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 267 #endif 268 #endif 269 270 /* SPL QSPI boot support */ 271 #ifdef CONFIG_SPL_SPI_SUPPORT 272 #define CONFIG_SPL_SPI_LOAD 273 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 274 #endif 275 276 /* SPL NAND boot support */ 277 #ifdef CONFIG_SPL_NAND_SUPPORT 278 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 279 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 280 #endif 281 282 /* 283 * Stack setup 284 */ 285 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR 286 287 /* Extra Environment */ 288 #ifndef CONFIG_SPL_BUILD 289 290 #ifdef CONFIG_CMD_DHCP 291 #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) 292 #else 293 #define BOOT_TARGET_DEVICES_DHCP(func) 294 #endif 295 296 #ifdef CONFIG_CMD_PXE 297 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) 298 #else 299 #define BOOT_TARGET_DEVICES_PXE(func) 300 #endif 301 302 #ifdef CONFIG_CMD_MMC 303 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) 304 #else 305 #define BOOT_TARGET_DEVICES_MMC(func) 306 #endif 307 308 #define BOOT_TARGET_DEVICES(func) \ 309 BOOT_TARGET_DEVICES_MMC(func) \ 310 BOOT_TARGET_DEVICES_PXE(func) \ 311 BOOT_TARGET_DEVICES_DHCP(func) 312 313 #include <config_distro_bootcmd.h> 314 315 #ifndef CONFIG_EXTRA_ENV_SETTINGS 316 #define CONFIG_EXTRA_ENV_SETTINGS \ 317 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ 318 "bootm_size=0xa000000\0" \ 319 "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ 320 "fdt_addr_r=0x02000000\0" \ 321 "scriptaddr=0x02100000\0" \ 322 "pxefile_addr_r=0x02200000\0" \ 323 "ramdisk_addr_r=0x02300000\0" \ 324 BOOTENV 325 326 #endif 327 #endif 328 329 #endif /* __CONFIG_SOCFPGA_COMMON_H__ */ 330