1 /* 2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #ifndef __CONFIG_SOCFPGA_COMMON_H__ 7 #define __CONFIG_SOCFPGA_COMMON_H__ 8 9 /* Virtual target or real hardware */ 10 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET 11 12 /* 13 * High level configuration 14 */ 15 #define CONFIG_DISPLAY_BOARDINFO_LATE 16 #define CONFIG_CLOCKS 17 18 #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) 19 20 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 21 22 /* add target to build it automatically upon "make" */ 23 #define CONFIG_BUILD_TARGET "u-boot-with-spl.sfp" 24 25 /* 26 * Memory configurations 27 */ 28 #define CONFIG_NR_DRAM_BANKS 1 29 #define PHYS_SDRAM_1 0x0 30 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) 31 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 32 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE 33 #if defined(CONFIG_TARGET_SOCFPGA_GEN5) 34 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 35 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 36 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 37 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 38 #define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */ 39 #endif 40 #define CONFIG_SYS_INIT_SP_OFFSET \ 41 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 42 #define CONFIG_SYS_INIT_SP_ADDR \ 43 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 44 45 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 46 47 /* 48 * U-Boot general configurations 49 */ 50 #define CONFIG_SYS_LONGHELP 51 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ 52 /* Print buffer size */ 53 #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ 54 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 55 /* Boot argument buffer size */ 56 #define CONFIG_AUTO_COMPLETE /* Command auto complete */ 57 #define CONFIG_CMDLINE_EDITING /* Command history etc */ 58 59 #ifndef CONFIG_SYS_HOSTNAME 60 #define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD 61 #endif 62 63 /* 64 * Cache 65 */ 66 #define CONFIG_SYS_L2_PL310 67 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS 68 69 /* 70 * EPCS/EPCQx1 Serial Flash Controller 71 */ 72 #ifdef CONFIG_ALTERA_SPI 73 #define CONFIG_SF_DEFAULT_SPEED 30000000 74 /* 75 * The base address is configurable in QSys, each board must specify the 76 * base address based on it's particular FPGA configuration. Please note 77 * that the address here is incremented by 0x400 from the Base address 78 * selected in QSys, since the SPI registers are at offset +0x400. 79 * #define CONFIG_SYS_SPI_BASE 0xff240400 80 */ 81 #endif 82 83 /* 84 * Ethernet on SoC (EMAC) 85 */ 86 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) 87 #define CONFIG_DW_ALTDESCRIPTOR 88 #define CONFIG_MII 89 #endif 90 91 /* 92 * FPGA Driver 93 */ 94 #ifdef CONFIG_CMD_FPGA 95 #define CONFIG_FPGA_COUNT 1 96 #endif 97 98 /* 99 * L4 OSC1 Timer 0 100 */ 101 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */ 102 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS 103 #define CONFIG_SYS_TIMER_COUNTS_DOWN 104 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) 105 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 106 #define CONFIG_SYS_TIMER_RATE 2400000 107 #else 108 #define CONFIG_SYS_TIMER_RATE 25000000 109 #endif 110 111 /* 112 * L4 Watchdog 113 */ 114 #ifdef CONFIG_HW_WATCHDOG 115 #define CONFIG_DESIGNWARE_WATCHDOG 116 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS 117 #define CONFIG_DW_WDT_CLOCK_KHZ 25000 118 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 30000 119 #endif 120 121 /* 122 * MMC Driver 123 */ 124 #ifdef CONFIG_CMD_MMC 125 #define CONFIG_BOUNCE_BUFFER 126 /* FIXME */ 127 /* using smaller max blk cnt to avoid flooding the limited stack we have */ 128 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ 129 #endif 130 131 /* 132 * NAND Support 133 */ 134 #ifdef CONFIG_NAND_DENALI 135 #define CONFIG_SYS_MAX_NAND_DEVICE 1 136 #define CONFIG_SYS_NAND_ONFI_DETECTION 137 #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS 138 #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS 139 #endif 140 141 /* 142 * I2C support 143 */ 144 #define CONFIG_SYS_I2C 145 #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS 146 #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS 147 #define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS 148 #define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS 149 /* Using standard mode which the speed up to 100Kb/s */ 150 #define CONFIG_SYS_I2C_SPEED 100000 151 #define CONFIG_SYS_I2C_SPEED1 100000 152 #define CONFIG_SYS_I2C_SPEED2 100000 153 #define CONFIG_SYS_I2C_SPEED3 100000 154 /* Address of device when used as slave */ 155 #define CONFIG_SYS_I2C_SLAVE 0x02 156 #define CONFIG_SYS_I2C_SLAVE1 0x02 157 #define CONFIG_SYS_I2C_SLAVE2 0x02 158 #define CONFIG_SYS_I2C_SLAVE3 0x02 159 #ifndef __ASSEMBLY__ 160 /* Clock supplied to I2C controller in unit of MHz */ 161 unsigned int cm_get_l4_sp_clk_hz(void); 162 #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000) 163 #endif 164 165 /* 166 * QSPI support 167 */ 168 /* Enable multiple SPI NOR flash manufacturers */ 169 #ifndef CONFIG_SPL_BUILD 170 #define CONFIG_SPI_FLASH_MTD 171 #define CONFIG_MTD_DEVICE 172 #define CONFIG_MTD_PARTITIONS 173 #endif 174 /* QSPI reference clock */ 175 #ifndef __ASSEMBLY__ 176 unsigned int cm_get_qspi_controller_clk_hz(void); 177 #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() 178 #endif 179 180 /* 181 * Designware SPI support 182 */ 183 184 /* 185 * Serial Driver 186 */ 187 #define CONFIG_SYS_NS16550_SERIAL 188 #define CONFIG_SYS_NS16550_REG_SIZE -4 189 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 190 #define CONFIG_SYS_NS16550_CLK 1000000 191 #elif defined(CONFIG_TARGET_SOCFPGA_GEN5) 192 #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS 193 #define CONFIG_SYS_NS16550_CLK 100000000 194 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) 195 #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART1_ADDRESS 196 #define CONFIG_SYS_NS16550_CLK 50000000 197 #endif 198 #define CONFIG_CONS_INDEX 1 199 200 /* 201 * USB 202 */ 203 204 /* 205 * USB Gadget (DFU, UMS) 206 */ 207 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) 208 #define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024) 209 #define DFU_DEFAULT_POLL_TIMEOUT 300 210 211 /* USB IDs */ 212 #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 213 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 214 #endif 215 216 /* 217 * U-Boot environment 218 */ 219 #if !defined(CONFIG_ENV_SIZE) 220 #define CONFIG_ENV_SIZE (8 * 1024) 221 #endif 222 223 /* Environment for SDMMC boot */ 224 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET) 225 #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ 226 #define CONFIG_ENV_OFFSET (34 * 512) /* just after the GPT */ 227 #endif 228 229 /* Environment for QSPI boot */ 230 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET) 231 #define CONFIG_ENV_OFFSET 0x00100000 232 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 233 #endif 234 235 /* 236 * mtd partitioning for serial NOR flash 237 * 238 * device nor0 <ff705000.spi.0>, # parts = 6 239 * #: name size offset mask_flags 240 * 0: u-boot 0x00100000 0x00000000 0 241 * 1: env1 0x00040000 0x00100000 0 242 * 2: env2 0x00040000 0x00140000 0 243 * 3: UBI 0x03e80000 0x00180000 0 244 * 4: boot 0x00e80000 0x00180000 0 245 * 5: rootfs 0x01000000 0x01000000 0 246 * 247 */ 248 249 /* 250 * SPL 251 * 252 * SRAM Memory layout: 253 * 254 * 0xFFFF_0000 ...... Start of SRAM 255 * 0xFFFF_xxxx ...... Top of stack (grows down) 256 * 0xFFFF_yyyy ...... Malloc area 257 * 0xFFFF_zzzz ...... Global Data 258 * 0xFFFF_FF00 ...... End of SRAM 259 */ 260 #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR 261 #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE 262 263 /* SPL SDMMC boot support */ 264 #ifdef CONFIG_SPL_MMC_SUPPORT 265 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) 266 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" 267 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 268 #endif 269 #else 270 #ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 271 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 272 #endif 273 #endif 274 275 /* SPL QSPI boot support */ 276 #ifdef CONFIG_SPL_SPI_SUPPORT 277 #define CONFIG_SPL_SPI_LOAD 278 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 279 #endif 280 281 /* SPL NAND boot support */ 282 #ifdef CONFIG_SPL_NAND_SUPPORT 283 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 284 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 285 #endif 286 287 /* 288 * Stack setup 289 */ 290 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR 291 292 /* Extra Environment */ 293 #ifndef CONFIG_SPL_BUILD 294 #include <config_distro_defaults.h> 295 296 #ifdef CONFIG_CMD_DHCP 297 #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) 298 #else 299 #define BOOT_TARGET_DEVICES_DHCP(func) 300 #endif 301 302 #ifdef CONFIG_CMD_PXE 303 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) 304 #else 305 #define BOOT_TARGET_DEVICES_PXE(func) 306 #endif 307 308 #ifdef CONFIG_CMD_MMC 309 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) 310 #else 311 #define BOOT_TARGET_DEVICES_MMC(func) 312 #endif 313 314 #define BOOT_TARGET_DEVICES(func) \ 315 BOOT_TARGET_DEVICES_MMC(func) \ 316 BOOT_TARGET_DEVICES_PXE(func) \ 317 BOOT_TARGET_DEVICES_DHCP(func) 318 319 #include <config_distro_bootcmd.h> 320 321 #ifndef CONFIG_EXTRA_ENV_SETTINGS 322 #define CONFIG_EXTRA_ENV_SETTINGS \ 323 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ 324 "bootm_size=0xa000000\0" \ 325 "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ 326 "fdt_addr_r=0x02000000\0" \ 327 "scriptaddr=0x02100000\0" \ 328 "pxefile_addr_r=0x02200000\0" \ 329 "ramdisk_addr_r=0x02300000\0" \ 330 BOOTENV 331 332 #endif 333 #endif 334 335 #endif /* __CONFIG_SOCFPGA_COMMON_H__ */ 336